Hardware Features - 3Com EtherLink 3C985B-SX User Manual

12 C
HAPTER

Hardware Features

Interoperability
Compliance with PCI Local
Bus Specification Version 2.0
and 2.1
Full-duplex Gigabit Ethernet
interface
Frame-based flow control
Gigabit Ethernet
fiber interface
Adaptive interrupt frequency The 3C985B-SX server NIC driver intelligently adjusts
Dual DMA channels
ASIC with on-chip MAC
and RISC processor
Universal dual-voltage
signaling
Status LEDs
Diagnostic support
1: I
NTRODUCTION
Operates with existing Ethernet equipment
Compatible with a 32- or 64-bit, 33/66 MHz
PCI bus master slot. As a bus master NIC, the NIC
requests access to the PCI bus instead of waiting to
be polled by the host. An innovative DMA algorithm
enables the 3C985B-SX server NIC to automatically
learn and conform to a particular host's PCI bus
and memory system requirements, maximizing
performance and host efficiency.
IEEE 802.3z
IEEE 802.3x
62.5/125 µm or 50/125 µm multimode fiber, using a
duplex SC connector
host interrupt frequency based on traffic conditions
to increase overall application throughput. In light
traffic, the NIC driver interrupts the host for each
received packet, minimizing latency. When traffic is
heavy, the NIC issues one host interrupt for multiple,
back-to-back incoming packets, preserving host
CPU cycles.
The PCI interface on the 3C985B-SX server NIC
contains two independent DMA channels for
simultaneous read and write operations.
The core control for the 3C985B-SX server NIC
resides in a tightly integrated, high-performance
ASIC. Embedded RISC processors in the ASIC provide
the flexibility to add new features to the NIC and
adapt it to future changes in network requirements
through software downloads. This embedded RISC
processor enables NIC drivers to exploit built-in
functions on the NIC that offload operations
from the host to the NIC.
3.3 V and 5 V
LINK and DATA
Diagnostics programs run under DOS or Windows NT.