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Intel
IXP2400/IXP2800 Network Processors
A.4.7
Transfer Register D Out .............................................................................................. 279
A.4.8
Next Neighbor Registers ............................................................................................. 280
A.5
CSRs ............................................................................................................................... 280
®
A.6
A.7
IXP2400 and IXP2800 Transactor States ....................................................................... 281
A.8
Transactor States for PCI Pins ........................................................................................ 285
B
Developer Workbench Shortcuts ....................................................................................... 289
B.1
Introduction...................................................................................................................... 289
Intel XScale® Core Memory Bus Functional Model .......................................................... 295
C.1
Summary of APIs ............................................................................................................ 295
C.1.1
XACT_IO API .............................................................................................................. 296
C.1.2
simRead32 / simWrite32 ............................................................................................. 296
C.1.3
cmbIntConnect/cmbIntEnable/cmbIntDisable ............................................................. 296
C.1.4
cmbIntDisableFIQ ....................................................................................................... 297
C.1.5
IS_CMB_ADDR_RESERVED / IS_CMB_INT_RESERVED....................................... 297
C.1.6
Additional CMB_IO API............................................................................................... 298
C.1.7
cmbRead32 / cmbWrite32........................................................................................... 298
C.1.8
cmbSetCb ................................................................................................................... 299
C.1.9
cmbSwapRead32 / cmbSwapWrite32......................................................................... 299
C.1.10 cmbBFMRead32 / cmbBFMWrite32 ........................................................................... 300
C.2
ENUMs ............................................................................................................................ 301
C.3
Defines ............................................................................................................................ 301
D
PCI Bus Functional Model ................................................................................................. 303
D.1
Loading the BFM ............................................................................................................. 303
D.2
Initializing the BFM .......................................................................................................... 303
D.3
Creating a Device ............................................................................................................ 303
D.4
Calling Console Functions from Another Foreign Model ................................................. 304
D.5
Setting a Callback Function............................................................................................. 304
D.6
Header file pciconfx.h ...................................................................................................... 304
E
SPI4 Bus Functional Model ............................................................................................... 311
E.1
Overview ......................................................................................................................... 311
E.2
SPI4 BFM Help................................................................................................................ 311
E.3
Console Functions........................................................................................................... 312
E.3.1
Device/Port Configuration ........................................................................................... 312
E.3.1.1spi4_define_device .......................................................................................... 312
E.3.1.2spi4_set_device_X_param/spi4_set_port_X_param ....................................... 313
E.3.1.3spi4_create_device.......................................................................................... 314
E.3.1.4spi4_connect_device ....................................................................................... 314
E.3.1.5spi4_enable_X ................................................................................................. 314
E.3.2
Simulation Control....................................................................................................... 315
E.3.2.1spi4_set_X_stop_control ................................................................................. 315
E.3.2.2spi4_set_sim_options ...................................................................................... 315
E.3.3
Flow Control ................................................................................................................ 316
E.3.3.1spi4_set_rx_fc_info/spi4_set_tx_fc_info/spi4_set_rx_calendar/
spi4_set_tx_calendar .................................................................................................. 316
xii
Memory Map Access................................................................................. 280
Development Tools User's Guide
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