Global Performance Monitors; Global Pmon Global Control/Status Registers; Table 2-1. Global Performance Monitoring Control Msrs - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

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a) Clear all uncore counters: Set U_MSR_PMON_GLOBAL_CTL.rst_all to 1.
b) Clear all overflow bits. When an overflow bit is cleared, all bits that summarize that overflow (above
in the hierarchy) will also be cleared. Therefore it is only necessary to clear the overflow bits
corresponding to the actual counter.
i.e. If counter 3 in B-Box 1 overflowed, to clear the overflow bit software should set
B_MSR_PMON_GLOBAL_OVF_CTL.clr_ov[3] to 1 in B-Box 1. This action will also clear
S_MSR_PMON_SUMMARY.ov_mb in S-Box 1 and U_MSR_PMON_GLOBAL_STATUS.ov_s1.c
c) Create the next sample: Reinitialize the sample by setting the monitoring data register to (2^48 -
sample_interval). Or set up a new sample interval as outlined in
Session".
d) Re-enable counting: Set U_MSR_PMON_GLOBAL_CTL.en_all to 1. Set the .rst_all field back to 0 with
the same write.
2.1.5

Global Performance Monitors

U_MSR_PMON_GLOBAL_OVF_CTL
U_MSR_PMON_GLOBAL_STATUS
U_MSR_PMON_GLOBAL_CTL
2.1.5.1

Global PMON Global Control/Status Registers

The following registers represent state governing all PMUs in the uncore, both to exert global control
and collect box-level information.
U_MSR_PMON_GLOBAL_CTL contains bits that can reset (.rst_all) and freeze/enable (.en_all) all the
uncore counters. The .en_all bit must be set to 1 before any uncore counters will collect events.
Note: The register also contains the enable for the U-Box counters.
If an overflow is detected in any of the uncore's PMON registers, it will be summarized in
U_MSR_PMON_GLOBAL_STATUS. This register accumulates overflows sent to it from the U-Box, W-Box
and S-Boxes and indicates if a disable was received from one of the boxes. To reset the summary
overflow bits, a user must set the corresponding bits in the U_MSR_PMON_GLOBAL_OVF_CTL register.
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ERIES NCORE ROGRAMMING UIDE

Table 2-1. Global Performance Monitoring Control MSRs

MSR Name
UNCORE PERFORMANCE MONITORING
Section 2.1.2, "Setting up a Monitoring
MSR Size
Access
Address (bits)
RW_RW 0x0C02 32
RW_RO 0x0C01 32
RW_RO 0x0C00 32
Description
U-Box PMON Global Overflow Control
U-Box PMON Global Status
U-Box PMON Global Control
2-3