Quickpath Interconnect (Qpi); Figure 1.5 Examples Of Unsupported Cpu Combinations In A Cabinet - Fujitsu PRIMEQUEST 1000 Series General Description Manual

PRIMEQUEST 1000 Series General Description
CHAPTER 1 Product Overview
No.
(3) This is not supported because the partition has different types of CPU installed, even
though the CPUs mounted on each SB are of the same type.

FIGURE 1.5 Examples of unsupported CPU combinations in a cabinet

Hyper Threading Technology function
The PRIMEQUEST 1000 series supports the Hyper Threading Technology function (hyper-threading function).
The hyper-threading function is a technology that makes it appear, from the viewpoint of the operating system, as
if one processor core is functioning as multiple processor cores. Using this function often improves CPU
performance.
- For the PRIMEQUEST 1800E2 series, the function supports up to two threads per core and up to 20 threads
per 10-core CPU.
For the PRIMEQUEST 1800E, the function supports up to two threads per core and up to 16 threads per 8-
core CPU.
- The hyper-threading function is enabled or disabled from the UEFI Configure CPU menu. The default setting
is "Enabled."
Intelligent power technologies
The PRIMEQUEST 1000 series supports the following intelligent power technologies.
- Enhanced Halt State
This function reduces the CPU power consumption by lowering the core clock frequency ratio and core
voltage of the CPU in idle mode according to instructions from the operating system.
- Demand Based Switching
This function changes the CPU operating voltage and clock combination called P-State to reduce power
consumption.
- Turbo Boost Technology
When more than one CPU core is idle, this function raises the frequency of a running CPU core to higher
than the specified frequency, within the TDP (thermal design power) range.
1.4.2

QuickPath Interconnect (QPI)

The PRIMEQUEST 1000 series uses a high-speed system bus called QPI for communication between CPUs and
between a CPU and chip set.
Each CPU used in the PRIMEQUEST 1000 series contains a built-in QPI interface and memory controller. This
permits you to scale up the configuration by connecting CPUs via the QPI.
The QPI is checked using the CRC (Cyclic Redundancy Code). It has a function to resend data if an error occurs
or to degrade the bus width or change a path if a permanent fault occurs.
These functions in combination with the Memory Mirror function provide availability equivalent to that provided
by the system mirror function of the PRIMEQUEST 400/500/500A series.
Description
15 C122-B022-11EN