Fujitsu FR Family Instruction Manual page 291

Bcc:D (Branch Relative if Condition Satisfied)
.......................................................... 200
Branching Instructions
Examples of Processing Delayed Branching
Instructions........................................... 61
Examples of Processing Non-delayed Branching
Instructions........................................... 60
Examples of Programing Delayed Branching
Instructions........................................... 62
Overview of Branching with Delayed Branching
Instructions........................................... 58
Overview of Branching with Non-delayed Branching
Instructions........................................... 58
Restrictions on Interrupts during Processing of
Delayed Branching Instructions.............. 59
BTSTH
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
.......................................................... 119
BTSTL
BTSTL (Test Lower 4 Bits of Byte Data in Memory)
.......................................................... 118
Bypassing
Register Bypassing............................................. 56
Byte Order
Bit Order and Byte Order.................................... 10
C
CALL
CALL (Call Subroutine) ........................... 184, 185
CALL:D (Call Subroutine)........................ 196, 198
Carry Bit
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register) .................... 75
SUBC (Subtract Word Data in Source Register and
Carry Bit from Destination Register)....... 80
CCR
Condition Code Register (CCR: Bit 07 to bit 00)
............................................................ 21
CMP
CMP (Compare Immediate Data of Source Register
and Destination Register)....................... 83
CMP (Compare Word Data in Source Register and
Destination Register) ............................. 82
CMP2 (Compare Immediate Data and Destination
Register) .............................................. 84
Compare
CMP (Compare Immediate Data of Source Register
and Destination Register)....................... 83
CMP (Compare Word Data in Source Register and
Destination Register) ............................. 82
CMP2 (Compare Immediate Data and Destination
Register) .............................................. 84
Condition Code Register
ANDCCR (And Condition Code Register and
Immediate Data) ..................................235
Condition Code Register (CCR: Bit 07 to bit 00)
............................................................21
ORCCR (Or Condition Code Register and Immediate
Data) ..................................................236
Configuration
Configuration of the "MD" Register .....................30
FR Family Register Configuration........................14
Program Status Register Configuration .................19
Return Pointer Configuration ...............................26
Sample Configuration of an FR Family Device........3
Sample Configuration of the FR Family CPU..........4
Stack Pointer Configuration.................................28
Table Base Register Configuration .......................24
Vector Table Configuration .................................35
COPLD
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................228
COPOP
COPOP (Coprocessor Operation) .......................226
Coprocessor
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................228
COPOP (Coprocessor Operation) .......................226
COPST (Store 32-bit Data from Coprocessor Register
to Register) .........................................230
COPSV (Save 32-bit Data from Coprocessor Register
to Register) .........................................232
Coprocessor Error
Saving and Restoring Coprocessor Error Information
............................................................50
Coprocessor Error Trap
Conditions for Generation of Coprocessor Error Traps
............................................................49
Coprocessor Error Trap Operation........................49
Overview of Coprocessor Error Traps...................49
"PC" Values Saved for Coprocessor Error Traps
............................................................49
Results of Coprocessor Operations after a Coprocessor
Error Trap .............................................49
Coprocessor Not Found Trap
Conditions for Generation of Coprocessor Not Found
Traps ....................................................48
Coprocessor Not Found Trap Operation................48
Overview of Coprocessor Not Found Traps...........48
Coprocessor Not Present Traps
"PC" Values Saved for Coprocessor Not Present Traps
............................................................48
Coprocessor Register
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................228
COPST (Store 32-bit Data from Coprocessor Register
to Register) .........................................230
COPSV (Save 32-bit Data from Coprocessor Register
to Register) .........................................232
INDEX
275