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INDEX
Index
Numerics
20-bit Data
LDI:20 (Load Immediate 20-bit Data to Destination
Register)............................................. 148
32-bit Data
COPLD (Load 32-bit Data from Register to
Coprocessor Register).......................... 228
COPSV (Save 32-bit Data from Coprocessor Register
to Register) ......................................... 232
LDI:32 (Load Immediate 32-bit Data to Destination
Register)............................................. 147
4-bit Immediate Data
ADD (Add 4-bit Immediate Data to Destination
Register)............................................... 73
ADD2 (Add 4-bit Immediate Data to Destination
Register)............................................... 74
8-bit Data
LDI:8 (Load Immediate 8-bit Data to Destination
Register)............................................. 149
A
ADD
ADD (Add 4-bit Immediate Data to Destination
Register)............................................... 73
ADD (Add Word Data of Source Register to
Destination Register) ............................. 72
ADD2 (Add 4-bit Immediate Data to Destination
Register)............................................... 74
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register) .................... 75
ADDN (Add Immediate Data to Destination Register)
............................................................ 77
ADDN (Add Word Data of Source Register to
Destination Register) ............................. 76
ADDN2 (Add Immediate Data to Destination
Register)............................................... 78
ADDSP (Add Stack Pointer and Immediate Data)
.......................................................... 238
Alignment
Data Restrictions on Word Alignment .................. 11
Program Restrictions on Word Alignment ............ 11
AND
AND (And Word Data of Source Register to Data in
Memory) .............................................. 86
AND (And Word Data of Source Register to
Destination Register) ............................. 85
ANDB
ANDB (And Byte Data of Source Register to Data in
Memory) .............................................. 90
274
ANDCCR
ANDCCR (And Condition Code Register and
Immediate Data) ................................. 235
ANDH
ANDH (And Half-word Data of Source Register to
Data in Memory) .................................. 88
Arithmetic Shift
ASR (Arithmetic Shift to the Right Direction)
................................................. 144, 145
ASR2 (Arithmetic Shift to the Right Direction)
......................................................... 146
ASR
ASR (Arithmetic Shift to the Right Direction)
................................................. 144, 145
ASR2 (Arithmetic Shift to the Right Direction)
......................................................... 146
B
BANDH
BANDH (And 4-bit Immediate Data to Higher 4 Bits
of Byte Data in Memory) ..................... 108
BANDL
BANDL (And 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory)......................... 106
Bcc
Bcc (Branch Relative if Condition Satisfied) ...... 193
Bcc:D (Branch Relative if Condition Satisfied)
......................................................... 200
BEORH
BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of
Byte Data in Memory)......................... 116
BEORL
BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory)......................... 114
Bit Order
Bit Order and Byte Order.................................... 10
Bit Pattern
Relation between Bit Pattern "Rs" and Register Values
........................................................... 65
Relation between Bit Patterns "Ri" and "Rj" and
Register Values..................................... 64
BORH
BORH (Or 4-bit Immediate Data to Higher 4 Bits of
Byte Data in Memory)......................... 112
BORL
BORL (Or 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory)......................... 110
Branch
Bcc (Branch Relative if Condition Satisfied) ...... 193
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