Processor - Intergraph InterServe 9000 System Reference Manual

Processor

Each Pentium II Xeon processor is packaged in a single edge contact (SEC) cartridge. The
cartridge includes the processor core with an integrated 16 KB primary (L1) cache; the secondary
(L2) cache; a thermal plate; and a back cover.
The processor implements the MMX technology and maintains full backward compatibility with
the 8086, 80286, Intel386, Intel486, Pentium, and Pentium Pro processors. The processor's
numeric coprocessor significantly increases the speed of floating-point operations and complies
with ANSI/IEEE standard 754-1985.
Each SEC cartridge connects to the baseboard through a 330-pin Slot 2 edge connector. The
cartridge is secured by a retention module attached to the baseboard. Depending on configuration,
your system has one to four processors.
The processor external interface is multiprocessor (MP)-ready and operates at 100 MHz. The
processor contains a local advanced programmable interrupt controller (APIC) unit for interrupt
handling in multiprocessor and uniprocessor (UP) environments.
The L2 cache is located on the substrate of the SEC cartridge. The cache:
Includes burst pipelined synchronous static RAM (BSRAM)
Is offered in 512 KB and 1 MB configurations (2 MB available upon Intel offering)
Has ECC
Operates at the full core clock rate
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