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EOnCE Controller Registers
4.7.7 Core Command Register (CORE_CMD)
The CORE_CMD register is used to execute instructions in the core while in debug state. The external host
writes the instruction into the CORE_CMD register as described in
EOnCE Registers Through JTAG."
CORE_CMD and GO. After writing the instruction into the CORE_CMD register, the core executes it
without leaving debug state. If the EX bit in ECR is also set, debug state is exited after the instruction is
performed.
The format of the injected command is shown in Figure 4-19 below.
47
Bit
ImmB
14 bits
bits [0:13]
CORE_CMD
Prefix1
Instruction Bus (IB)
[15:0]
The length control bits are described in Table 4-17, below:
Length Control Bits
0
0
1
1
The two prefix bits allow the instruction to use the high bank of registers. Bits 15 and 14 in the second and
third words encode the grouping/word partition used by the core for execution set parsing. In the case of a
single instruction, they do not need to be part of the CORE_CMD word. For further details, see
Appendix A, "SC140 DSP Core Instruction Set."
In general, core commands should not perform illegal operations. In case a core command generated an
exception (such as an illegal exception), the exception will be serviced only after the core exits debug state.
4-48
The EOnCE commands written into the ECR must be Write
34 33
20 19
ImmA
14 bits
bits [0:13]
Prefix2
Opcode
[15:0]
[15:0]
Figure 4-19. Injected Instruction Format
Table 4-17. Length Control Bits
Description
0
Not supported
1
One word instruction
0
Two word instruction
1
Three word instruction
Section 4.2.6, "Reading/Writing
4
3
Opcode
16 bits
bits [0:15]
{Prefix1[5], Prefix1[7]}
ImmA
ImmB
[15:0]
[15:0]
SC140 DSP Core Reference Manual
2
1
Ext.
Length
Prefix
Control
2 bits
2 bits
0
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