Eonce Controller Block Diagram; Eonce Controller Register Set - Freescale Semiconductor SC140 DSP Core Reference Manual

• Reading and writing EOnCE registers from the software
• Real-time JTAG port access
• Real-time data transfer
• Executing instructions while in debug state
• Samples core PC information in various states
Figure 4-8 displays the EOnCE controller block diagram.
TCK
Command Register
TDI
TDO
Update Signal from the TAP Controller
The EOnCE controller register set is shown in Table 4-6.
Register Name
ECR
ESR
EMCR
ERCV
ETRSMT
EE_CTRL
CORE_CMD
PC_EXCP
SC140 DSP Core Reference Manual
Address
Decoder
Receive Register
Transmit Register
Figure 4-8. EOnCE Controller Block Diagram
Table 4-6. EOnCE Controller Register Set
Description
EOnCE command register
EOnCE status register
EOnCE monitor and control register
EOnCE receive register
EOnCE transmit register
EE signals control register
EOnCE core command register
PC of the execution set causing illegal or overflow exception
EOnCE Module Internal Architecture
6 0
Address
Monitor and Control Register
Status Register
Control
Logic
4-17