Event Selector Mask Disable Trace Register (Esel_Dtb); Trace Unit Registers; Trace Buffer Control Register (Tb_Ctrl) - Freescale Semiconductor SC140 DSP Core Reference Manual

4.10.5 Event Selector Mask Disable Trace Register
(ESEL_DTB)
This 16-bit register has one bit for every source of the ES. Setting the appropriate bit configures the related
source to cause a disable trace.
Figure 4-27 displays the bit configuration of ESEL_DTB.
BIT 15 14 13
DEBUGE
EE4 EE3
V
TYPE rw rw rw
RESET 0 0
Figure 4-27. Event Selector Mask Disable Trace (ESEL_DTB)
If multiple sources are configured to disable trace, they are ANDed or ORed according to the value of the
SELDTB bit in the ESEL_CTRL. See
for further details. If all the bits are set to zero, the ES does not issue a disable trace.
The same event cannot be configured to both enable and disable tracing.

4.11 Trace Unit Registers

The trace unit includes the following registers:
•

Trace Buffer Control Register (TB_CTRL)

• Trace Buffer Read Pointer Register (TB_RD)
• Trace Buffer Write Pointer Register (TB_WR)
• Trace Buffer Virtual Register (TB_BUFF)
4.11.1 Trace Buffer Control Register (TB_CTRL)
The TB_CTRL register controls the operation of the trace unit. The following tracing modes are possible,
all which trace the PC of execution sets that answer some conditions:
• TEXEXT -
• TMARK -
• TCHOF -
• TLOOP -
• TINT -
TEXEC and TMARK can only be activated on their own, without other tracing options enabled.
SC140 DSP Core Reference Manual
12 11 10
COUN
EE2 EE1 EE0
rw rw rw rw
0 0 0 0
Section 4.10.1, "Event Selector Control Register (ESEL_CTRL),"
trace the PC of every execution set
trace the PC of execution sets that includes the MARK instruction
trace the source and destination PC of execution set that includes
a taken COF instruction (listed in Table A-13 in Appendix A, not including
TRAP, but including the BREAK, CONT/D instructions)
trace the exection of HW loops.
For long loops, the PC of the last address (LA) and start address (SA) are traced.
For short loops, only the PC of LA is traced.
trace the interrupt point and destination PC of interrupts and exceptions
(including the TRAP, and ILLEGAL instructions)
9 8 7 6
EDCA EDCA
EDCD
T 7 6
rw rw rw
0 0 0 0
Trace Unit Registers
5 4 3 2
EDCA EDCA EDCA EDCA
5 4 3 2
rw rw rw rw
0 0 0 0
1 BIT 0
EDCA EDCA
1 0
rw rw
0 0
4-65