Channel Mirroring Mode; Demand And Patrol Scrub; Intel ® I/O Hub (Ioh) 5500 Chipset; Table 11. Intel Ioh 5500 Chipset Features - Intel SC5650BCDP Technical Product Specification

Intel Server Board S5500BC TPS
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The Intel Xeon processor 5500 series and 5600 series on sockets 1 and 2 in a dual-processor
configuration are completely autonomous. DIMMs routed to sockets are isolated and can be
initialized locally, including RAS configurations. The Intel
set of RAS questions in the BIOS Setup and can configure common RAS features across the
sockets. If one socket fails the RAS population requirements, the BIOS sets all channels to
Independent Channel mode. The rules on channel population and channel matching vary by the
RAS mode used. Note that support of RAS modes requires matching DIMM population between
channels (sparing, mirroring, and lockstep) requiring ECC DIMMs be populated.
You can populate channels in any order in Independent Channel Mode. You can populate both
channels in any order and have no matching requirements. All channels must run at the same
interface frequency, but individual channels may run at different DIMM timings (RAS latency,
CAS latency, and so forth).

3.2.5 Channel Mirroring Mode

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The Intel Xeon processor 5500 series and 5600 series supports channel mirroring to
configure the available channels of DDR3 DIMMs in a mirrored configuration. Unlike channel
sparing, the mirrored configuration is a redundant image of the memory and can continue to
operate when sporadic uncorrectable errors occur.

3.2.6 Demand and Patrol Scrub

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The Intel Integrated Memory Controller supports demand and patrol scrubbing. A scrub fixes a
correctable error in memory. A 4-byte ECC is attached to each 32-byte ―payload‖. An error is
detected when the ECC calculated from the payload does not match the ECC read from
memory. The error is corrected by modifying the ECC, payload, or both, and then writing both
the ECC and payload back to memory. Only one demand or patrol scrub can be completed at a
time. Patrol scrubs are intended to ensure that data with a correctable error does not remain in
DRAM long enough to cause further corruption and an uncorrectable particle error. The Intel
QuickPath Memory Controller issues a Patrol Scrub at a rate sufficient to write every line once a
day. The maximum is one scrub every 82 ms with 64 GB of memory.
3.3 Intel I/O Hub (IOH) 5500 chipset
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The Intel I/O Hub (IOH) 5500 chipset component provides a connection point between various
I/O components and Intel
the features supported by the chipset.
Intel
Chipset
Interconnect Ports
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Intel IOH 5500
chipset
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The Intel IOH 5500 chipset on the Intel
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
Two Intel QuickPath Interconnect interfaces with full-width links (20 lanes in each
direction).
Revision 1.8
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QuickPath Interconnect based processors. The following table shows
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Table 11. Intel IOH 5500 Chipset Features
QuickPath
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Intel Xeon
2 and Intel® Xeon processor 5600
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Server Board S5500BC have the following features:
Intel order number: E42249-009
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Server Board S5500BC provide one
Processor
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processor 5500 series
series
Functional Architecture
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PCI Express*
Manageability
Lanes
24 Node Manager
29