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Intel SE7500CW2 Technical Product Specification

Intel SE7500CW2 Technical Product Specification

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SE7500CW2 Server Board
Technical Product Specification
Intel Document Number C19122-001
Revision 1.40
February 2003
Enterprise Platforms and Services Marketing

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Summary of Contents for Intel SE7500CW2

  • Page 1 SE7500CW2 Server Board Technical Product Specification Intel Document Number C19122-001 Revision 1.40 February 2003 Enterprise Platforms and Services Marketing...
  • Page 2 Revision History SE7500CW2 Server Board Technical Product Specification Revision History Date Revision Modifications Number 5/29/2002 Initial release 6/06/2002 1.01 Minor technical and grammatical updates from review comments Updated BIOS menus, updated BIOS crisis recovery, added BIOS Beep 9/9/2002 1.10 codes, and MTBF testing results.
  • Page 3 Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 4: Table Of Contents

    Table of Contents SE7500CW2 Server Board Technical Product Specification Table of Contents 1. Introduction ..........................1 Audience..........................1 2. SE7500CW2 Server Board Overview...................2 SE7500CW2 Feature Set....................2 3. Functional Architecture......................4 Processor and Memory Subsystem...................4 3.1.1 Processor Support......................4 3.1.2 Memory Subsystem ......................6 Intel E7500 Chipset......................10 3.2.1...
  • Page 5 SE7500CW2 Server Board Technical Product Specification Table of Contents System Configuration and Initialization................31 6.2.1 Memory ........................31 6.2.2 Processors .........................34 6.2.3 Extended System Configuration Data (ESCD), Plug and Play (PnP)......35 6.2.4 Legacy ISA Configuration....................36 6.2.5 Automatic Detection of Video Adapters ..............36 6.2.6...
  • Page 6 BIOS Recovery Beep Codes ..................77 7.1.4 POST Error Codes and Messages ................77 7.1.5 Memory Error Codes ....................80 8. SE7500CW2 Connectors and Jumper Blocks ..............81 Main Power Connector .....................81 Memory Module Connector....................83 Processor Heat Syncs .....................84 Processor Socket......................84 System Management Headers..................87 8.5.1...
  • Page 7 Replacing the Back-Up Battery...................105 11. Mechanical Spefications....................106 11.1 Mechanical Specifications ...................106 Appendix A: SE7500CW2 Integration and Usage Tips ............CIX Appendix B: SE7500CW2Errata documentation ..............CXI 12. Errata ..........................CXII Status Intel is investigating the possibility of fixing this erratum........CXIV Glossary..........................
  • Page 8 List of Figures SE7500CW2 Server Board Technical Product Specification List of Figures Figure 1. SE7500CW2 Server Board Block Diagram ..............3 Figure 2. Memory Sub-system Block Diagram................6 Figure 3. Memory Bank Label Definition ..................8 Figure 4. ATA-100 RAID Level .......................18 Figure 5. SE7500CW2 Interrupt Routing Diagram (ICH3-S Internal) ..........24 Figure 6.
  • Page 9 Table 5. Video Modes ........................19 Table 6. PCI Interrupt Routing/Sharing ..................21 Table 7. Interrupt Definitions ......................22 Table 8. Monitored Componnets on Intel® Server Board SE7500CW2........27 Table 9: Allowed Combinations of Floppy Drive and Floppy Media ..........37 Table 10: Supported Wake Events ....................39 Table 11: Non-ASCII Key Mappings ....................43...
  • Page 10 List of Tables SE7500CW2 Server Board Technical Product Specification Table 32: Exit Menu........................67 Table 34: Security Features Operating Model ................69 Table 35: System ROM BIOS POST task point ................71 Table 36: Crisis Disk Boot Block BIOS POST task point..............75 Table 37: POST Error Beep Codes ....................76 Table 38.
  • Page 11 SE7500CW2 Server Board Technical Product Specification List of Tables Table 67. Turn On / Off Timing ....................101 Table 68. Transient Load Requirements ..................102 Table 69. Server Board Connector Specifications ..............107 Revision 1.40...
  • Page 12 List of Tables SE7500CW2 Server Board Technical Product Specification <This Page Intentionally Left Blank> Revision 1.40...

  • Page 13: Introduction

    Chapter 11: Mechanical Specifications Audience This document for technical personnel who want a technical overview of the SE7500CW2 server board. Familiarity with the personal computer, Intel server architecture, Intel processor architecture, memory technologies and the Peripheral Component Interconnect (PCI) local bus architecture is assumed.

  • Page 14: Se7500Cw2 Server Board Overview

    1 As of the writing of this document, testing with 2GB DIMM modules was not complete and therefore not yet supported. 2GB DIMM support would allow for up to 8GB of main memory on the SE7500CW2. For updates on support of 2GB DIMM modules, visit the SE7500CW2 support website at http://support.intel.com/support/motherboards/server/se7500cw2.

  • Page 15: Figure 1. Se7500Cw2 Server Board Block Diagram

    SSI-compliant connectors for SSI interface support: front panel and power connectors. The figure below shows the functional blocks of the server board and the plug-in modules that it supports. 4GB DDR200 or DDR266 memory Figure 1. SE7500CW2 Server Board Block Diagram Revision 1.40...

  • Page 16: Functional Architecture

    As of the writing of this document, testing with 2GB DIMM modules was not complete and therefore not yet supported. 2GB DIMM support would allow for up to 8GB of main memory on the SE7500CW2. For updates on support of 2GB DIMM modules, visit the SE7500CW2 support website at http://support.intel.com/support/motherboards/server/se7500cw2.
  • Page 17 3.1.1.1 Processor VRD The Intel Server Board SE7500CW2 has a single VRD (Voltage Regulator Down) to support two processors. It is compliant with the VRM 9.1 specification and provides a maximum of 130 AMPs, which is capable of supporting current supported processors as well as those supported in the future.

  • Page 18: Memory Subsystem

    As of the writing of this document, testing with 2GB DIMM modules was not complete and therefore not yet supported. 2GB DIMM support would allow for up to 8GB of main memory on the SE7500CW2. For updates on support of 2GB DIMM modules, visit the SE7500CW2 support website at http://support.intel.com/support/motherboards/server/se7500cw2.
  • Page 19 1 As of the writing of this document, testing with 2GB DIMM modules was not complete and therefore not yet supported. 2GB DIMM support would allow for up to 8GB of main memory on the SE7500CW2. For updates on support of 2GB DIMM modules, visit the SE7500CW2 support website at http://support.intel.com/support/motherboards/server/se7500cw2.

  • Page 20: Figure 3. Memory Bank Label Definition

    Functional Architecture SE7500CW2 Server Board Technical Product Specification • Interface: SSTL2 • Two DIMMs must be populated in a bank for a 144-bit wide memory data path. • Any or all memory banks may be populated Table 2. Memory Bank Labels...
  • Page 21 SE7500CW2 Server Board Technical Product Specification Functional Architecture Revision 1.40...

  • Page 22: Intel E7500 Chipset

    133-MHz Rev. 2.2 compliant PCI-X buses (implemented on Intel Server Board SE7500CW2 as one bus with one 64-bit, 133MHz slot and one bus with two 64-bit, 100MHz slots). The P64H2 is both master and target on both PCI-X buses.

  • Page 23: Mch Memory Architecture Overview

    As of the writing of this document, testing with 2GB DIMM modules was not complete and therefore not yet supported. 2GB DIMM support would allow for up to 8GB of main memory on the SE7500CW2. For updates on support of 2GB DIMM modules, visit the SE7500CW2 support website at http://support.intel.com/support/motherboards/server/se7500cw2.

  • Page 24: Mch North Bridge

    As of the writing of this document, testing with 2GB DIMM modules was not complete and therefore not yet supported. 2GB DIMM support would allow for up to 8GB of main memory on the SE7500CW2. For updates on support of 2GB DIMM modules, visit the SE7500CW2 support website at http://support.intel.com/support/motherboards/server/se7500cw2.

  • Page 25: Ich3-S

    PCI bus interface. On the Intel Server Board SE7500CW2, the primary role of the ICH3-S is to provide the gateway to all PC-compatible I/O devices and features. The Intel Server Board SE7500CW2 uses the following ICH3-S features: •...
  • Page 26 The ICH3-S contains three USB revision 1.1 controllers and four USB hubs. The USB controller moves data between main memory and the six USB connectors. All six ports function identically and with the same bandwidth. The Intel Server Board SE7500CW2 implements 4 of the 6 ports on the board.

  • Page 27: Super I/O

    • “Wake-on” control 3.3.1 Serial Ports The SE7500CW2 server board provides two serial ports, an external serial port, and an internal serial header. The following sections provide details on the use of the serial ports. 3.3.1.1 Serial 1 Serial 1 is a standard DB9 interface located at the rear I/O panel of the server board, to the left of the video connector below the parallel port connector.

  • Page 28: Bios Flash

    3.3.2 BIOS Flash The SE7500CW2 server board incorporates an Intel® N82802AC (FWH8) Flash memory component. The N82802AC is a high-performance 8-megabit memory component that provides 1024K x 8 of BIOS and non-volatile storage space. The flash device is connected through the LPC Bus from the ICH3-S from the SIO.

  • Page 29: Included Pci Devices

    ® The Intel Server Board SE7500CW2 provides an embedded dual channel ATA-100 bus through the use of the Promise* Technology PDC20267 ASIC. The PDC20267 ATA-100 controller contains two independent ATA-100 channels that share a single 32-bit, 33-MHz PCI bus master interface as a multifunction device, packaged in a 128-pin PQFP.

  • Page 30: Video Controller

    Video Controller ® The Intel Server Board SE7500CW2 provides an ATI Rage XL PCI graphics accelerator, along with 8 MB of video SDRAM and support circuitry for an embedded SVGA video subsystem. The Revision 1.40...

  • Page 31: Table 5. Video Modes

    CRT and LCD monitors up to 100 Hz vertical refresh rate. ® The Intel Server Board SE7500CW2 provides a standard 15-pin VGA connector and supports disabling of the on-board video through the BIOS setup menu or when a plug in video card is installed in any of the PCI slots.

  • Page 32: Network Interface Controller (Nic)

    Network Interface Controller (NIC) The SE7500CW2 server board supports two 10Base-T/100Base-TX Network Interface Controllers (NICs) based on the Intel 82550PM NIC. The 82550PM is a highly integrated PCI LAN controller in a thin BGA 15mm package. The controller’s baseline functionality is equivalent to that of the Intel 82559, with the addition of Alert-on-LAN functionality.

  • Page 33: Interrupt Routing

    Signal Name LED1_L LED1_L Interrupt Routing The SE7500CW2 interrupt architecture accommodates both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O APICs in the ICH3-S. 4.5.1 Legacy Interrupt Routing For PC-compatible mode, the ICH3-S provides two 82C59-compatible interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary interrupt controller (standard PC configuration).

  • Page 34: Apic Interrupt Routing

    Intel I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA compatibility interrupts IRQ(0-15). When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire serial interface to the local APICs.

  • Page 35: Irq Scan For Pciirq

    The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with the standard implementation using the minimum 17 sampling channels. The Intel Server Board SE7500CW2 has an external PCI interrupt serializer for PCIIRQ scan mechanism of ICH3-S to support 16 PCI IRQs.

  • Page 36: Figure 5. Se7500Cw2 Interrupt Routing Diagram (Ich3-S Internal)

    Hub-Link B INTR IRQ1 HI2.0 INTERFACE IRQ2 IRQ3 IRQ4 CPU2 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 P64H2 IRQ10 IRQ11 IRQ12 IOAPIC 2 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 Figure 5. SE7500CW2 Interrupt Routing Diagram (ICH3-S Internal) Revision 1.40...

  • Page 37: Figure 6. Se7500Cw2 Interrupt Routing Diagram

    SE7500CW2 Server Board Technical Product Specification Included PCI Devices Super I/O Timer Keyboard Cascade Serial Port2/ISA SERIRQ SERIRQ_H Serial Port1/ISA Floppy/ISA SCI/ISA Mouse/ISA Coprocessor Error P_IDE/ISA Not Used PIRQA# P64H2-A PIRQB# SLOT-4 -A/C# PIRQC# SLOT-4 -B/D# PIRQD# SLOT-5 -A/C# PIRQE#...

  • Page 38: Figure 7. Se7500Cw2 Pci Interrupt Mapping Diagram

    ICH3 ICH3 ICH3 ICH3 ICH3 ICH3 ICH3 ICH3 PIRQH# PIRQA# PIRQD# PIRQC# PIRQG# PIRQB# PIRQE# PIRQF# NIC2 NIC1 P64H2 BT_INTR# Note: P1 is P64H2 PCI-bus A, P2 is P64H2 PCI-bus B Figure 7. SE7500CW2 PCI Interrupt Mapping Diagram Revision 1.40...

  • Page 39: Hardware Monitoring

    These controllers use the I C bus to communicate to all the sensors integrated on the baseboard. Below is a table of monitored headers and sensors on the Intel Server Board SE7500CW2. Table 9. Monitored Componnets on Intel® Server Board SE7500CW2 Item...

  • Page 40: Figure 8 Intel ® Server Board Se7500Cw2 Hardware Monitoring

    Hardware Monitoring SE7500CW2 Server Board Technical Product Specification Ambient Temperature VTIN1 CPU1 (604 pins) VTIN2 Temperature Sensor 2 High Byte (Index 50h, Bank 1) CPU2 (604 pins) VTIN3 Temperature Sensor 3 High Byte (Index 50h, Bank 2) Vcpu VCOREA (Index 20h) VCOREB (Index 21h) +1.8V...
  • Page 41 SE7500CW2 Server Board Technical Product Specification Hardware Monitoring Revision 1.40...

  • Page 42: Intel Landesk Client Manager

    Please check this web site for updates to the software prior to installing and using it. Additionally, documentation on how to install and use the LDCM software is provided on the SE7500CW2 resource CD and on the support website at this URL.

  • Page 43: System Bios

    The flash ROM contains system initialization routines, the BIOS Setup Utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. The flash ROM also contains initialization code in compressed form for on-board peripherals, like ATA-100 RAID, PXE ROM and video controllers.
  • Page 44 6.2.1.1 Memory Configuration The SE7500CW2 server board uses the Intel E7500 MCH chipset to configure the system baseboard memory The SE7500CW2 server BIOS is responsible for configuring and testing the system memory. The configuration of the system memory involves probing the memory modules for their characteristics and programming the chipset for optimum performance.
  • Page 45 EEPROM or Serial Presence Detect (SPD) of each DIMM. The memory system is based on rows. Since the SE7500CW2 server board supports dual channel memory, DIMMs must be populated in pairs with the same size. This means two DIMMs are required to constitute a row.

  • Page 46: Processors

    6.2.2.1 Processor Initialization The SE7500CW2 server board can support up to two Intel® Xeon™ processor with 512KB L2 Cache processors. The system BIOS must perform the various initialization sequences to program each processor cache, APIC and MTRRs. Revision 1.40...

  • Page 47: Extended System Configuration Data (Escd), Plug And Play (Pnp)

    (also called the “update”). The BIOS is responsible for storing the update in a non-volatile memory block and loading it into each processor during the POST sequence. The Intel Xeon processor with 512KB L2 Cache processor has the same capability for updating the processor microcode as previous Intel processors. The SE7500CW2 server board supports all microcode patches available for the supported processor steppings, plus an additional two empty slots are available for updates.

  • Page 48: Legacy Isa Configuration

    System BIOS SE7500CW2 Server Board Technical Product Specification Beginning at the lowest device, the BIOS uses a “depth-first” scan algorithm to enumerate the PCI buses. Each time a bridge device is located, the bus number is incremented and scanning continues on the secondary side of the bridge until all devices on the current bus are scanned.

  • Page 49: Floppy Drives

    IBM* XT/AT standards. Most floppy controllers have support for two floppy drives although such configurations are rare. At a minimum, the SE7500CW2 BIOS supports 1.44 MB and 2.88 MB floppy drives. LS-120 floppy drives are attached to the IDE controller and are covered elsewhere.

  • Page 50: Bios Supported Server Management Features

    BIOS Supported Server Management Features The SE7500CW2 server BIOS supports many standards-based server management features and several proprietary features. This section describes the implementation of the standard and the proprietary features including console redirection, The BIOS owns console redirection over a serial port.

  • Page 51: Wake Events

    The ACPI BIOS also provides the ACPI Description Tables. The SE7500CW2 server platform supports S0, S4, and S5 states. The ACPI specification defines the sleep states and requires the system to support at least one of them.
  • Page 52 System BIOS SE7500CW2 Server Board Technical Product Specification Ring indicate from COM- Wakeup from S4/S5 if the system in the S4/S5 state Ring indicate from COM- Wake up from S4/S5 if system in the S4/S5 state If COM-B is used for emergency management port, COM-B wakeup is disabled.

  • Page 53: Wired For Management (Wfm)

    SE7500CW2 Server Board Technical Product Specification System BIOS to place the system in the On state. The OS retains control of the system and OS policy determines the sleep state, if any, and the sleep sources from which the system can wake.

  • Page 54: Console Redirection

    UMB space by approximately 32 KB. This is sufficient to compromise or even prevent successful operation of some downloaded programs The SE7500CW2 server board is compliant with PXE 2.1. It implements the Post Memory Manager Specification v1.01.

  • Page 55: Table 11: Non-Ascii Key Mappings

    SE7500CW2 Server Board Technical Product Specification System BIOS During console redirection, the remote terminal sends keystrokes to the local server. The remote terminal may be a dumb terminal or a system with a modem running a communication program, such as ProComm*. The local server passes video back over the same link.

  • Page 56: Serial Ports

    Software bypasses this handler does not receive redirected keystrokes. 6.3.5 Serial Ports The SE7500CW2 server board has two serial ports, an internal 9-pin header for COM2, and an external COM1 serial port that can be used. Refer to sections 3.3 and 8.13 for additional serial port information.

  • Page 57: System Management Bios (Smbios)

    The system administrator can use SMBIOS to obtain the types, capabilities, operational status, installation date, and other information about the system components. The SE7500CW2 BIOS provides the SMBIOS structures via a table-based method. The table convention, provided as an alternative to the calling interface, allows the SMBIOS structures to be accessed under 32-bit protected-mode operating systems such as Windows 2000*.

  • Page 58: Windows* Compatibility

    For example, a server system used in small home/office environments has different requirements than one which is used for enterprise applications. The SE7500CW2 server BIOS meets the applicable requirements as specified in version 3.0 of the HDG specification. 6.3.7.1 Quiet Boot Version 3.0 of the Hardware Design Guide for Windows NT requires that the BIOS provide...

  • Page 59: Bios Serviceability Features

    The BIOS may temporarily remove the splash screen when the user is prompted for a password during POST. The BIOS also allows an OEM to override the standard Intel splash screen with a custom one. The OEM logo replacing procedure is below.

  • Page 60: Flash Update Utility

    System BIOS SE7500CW2 Server Board Technical Product Specification Note: If the jumper is not removed and the machine is powered on, then the BIOS fail with 3 long beeps, wait 3 seconds, and then repeat the cycle. 6.4.1 Flash Update Utility The Flash Memory Update utility (Phlash.exe) loads a fresh copy of the BIOS into flash ROM.
  • Page 61 SE7500CW2 Server Board Technical Product Specification System BIOS 8) Execute A:> 2.bat 9) There are two ways to update Flash Memory or System BIOS. A) The first is to highlight the option that reads “Update Flash Memory from a File”...

  • Page 62: Bios And Bios Setup

    System BIOS SE7500CW2 Server Board Technical Product Specification 2) Force Recovery Mode: a. Shutdown the system and unplug the power cable. b. Insert the jumper into pin 3-4 of the J106 connector on the baseboard. This connector is near the onboard NICs. Refer to the Quick Start Guide if you need further assistance locating it.

  • Page 63: Entering The Bios Setup Utility

    SE7500CW2 Server Board Technical Product Specification System BIOS as described in this section, may be different from those observed on any one pre-production version of the system BIOS. This section will be updated in the 1.0 release of this document.
  • Page 64 System BIOS SE7500CW2 Server Board Technical Product Specification Exit The ESC key provides a mechanism for backing out of any field. This key will undo the pressing of the Enter key. When the ESC key is pressed while editing any field or selecting features of a menu, the parent menu is re-entered.

  • Page 65: Menu Selection Bar

    SE7500CW2 Server Board Technical Product Specification System BIOS 6.5.4 Menu Selection Bar The Menu Selection Bar is located at the top of the screen and displays the major menu selections available to the user. The menu bar is shown below.

  • Page 66: Table 18: Primary/Secondary, Master/Slave Submenu

    System BIOS SE7500CW2 Server Board Technical Product Specification 6.5.5.1 Primary/Secondary, Master/Slave Submenus To access this sub-menu select Main on the menu bar and then the master or slave to be configured. Main Advanced Security Power Boot System Exit Primary Master...

  • Page 67: Advanced Menu

    SE7500CW2 Server Board Technical Product Specification System BIOS 6.5.6 Advanced Menu To access this menu, select Advanced on the menu bar at the top of the screen. Main Advanced Security Power Boot System Exit I/O Device Configuration On Board Device...
  • Page 68 Enabled (default) 6.0 SP1. PXE Support Disabled (default) Enables support for onboard PXE. NIC2 NIC1 Hyper-Threading Disabled Allows Intel Xeon processors to run in hyper- threading mode. Enabling this setting will improve Enabled (default) throughput significantly on certain applications. Revision 1.40...

  • Page 69: Table 20: I/O Device Configuration Submenu

    SE7500CW2 Server Board Technical Product Specification System BIOS 6.5.6.1 I/O Device Configuration Submenu To access this submenu, select Advanced on the menu bar at the top of the screen and then I/O Device Configuration. Main Advanced Security Power Boot System...

  • Page 70: On Board Device Submenu

    System BIOS SE7500CW2 Server Board Technical Product Specification Feature Choices Description Mode Output only Sets the mode for the parallel port. (This feature is present Bi-directional Output only is the standard printer connection only when Parallel Port is mode. set to enabled) Bi-directional is the standard bidirectional mode.

  • Page 71: Table 21: On Board Device Submenu

    SE7500CW2 Server Board Technical Product Specification System BIOS Table 22: On Board Device Submenu Choices or Display Feature Only Description Onboard RAID Disabled Enables the onboard PCI Promise PDC20267 controller. Enabled (default) Onboard NIC 1 Disabled Enables the onboard PCI Intel 82550PM Controller (Device 5).

  • Page 72: Table 23. Option Rom Scan Submenu

    System BIOS SE7500CW2 Server Board Technical Product Specification PCI Device, Slot #2 Select to Configures the specific PCI device expansion ROM.. display submenu PCI Device, Slot #3 Select to Configures the specific PCI device expansion ROM.. display submenu PCI Device, Slot #4 Select to Configures the specific PCI device expansion ROM..

  • Page 73: Table 25: Console Redirection Submenu

    SE7500CW2 Server Board Technical Product Specification System BIOS (default) 6.5.6.5 Console Redirection Submenu To access this submenu, select Advanced on the menu bar at the top of the screen and then Console Redirection. Main Advanced Security Power Boot System Exit...

  • Page 74: Table 26: Event Logging Submenu

    System BIOS SE7500CW2 Server Board Technical Product Specification Feature Choices Description Console Connection Direct Indicates whether the console is connected directly to the (default) system or whether a modem is used. modem Continue C.R. after Enables console redirection (C.R.) after the operating...

  • Page 75: Table 27: Hardware Monitor Submenu

    SE7500CW2 Server Board Technical Product Specification System BIOS 6.5.6.7 Hardware Monitor Submenu To access this submenu, select Advanced on the menu bar at the top of the screen and then Hardware Monitor. Main Advanced Security Power Boot System Exit I/O Device Configuration...

  • Page 76: Security Menu

    System BIOS SE7500CW2 Server Board Technical Product Specification 6.5.7 Security Menu To access this menu, select Security on the menu bar at the top of the screen. Main Advanced Security Power Boot System Exit Table 29 lists the options available on the Security menu. Enabling the Supervisor Password field requires a password for entering Setup.

  • Page 77: Power Menu

    SE7500CW2 Server Board Technical Product Specification System BIOS 6.5.8 Power Menu To access this menu, select Power on the menu bar at the top of the screen. Main Advanced Security Power Boot System Exit Table 30 lists the options available on the Power menu. This menu is designed to disable ACPI automatic reboot in the S0 or S4 states.

  • Page 78: System Menu

    System BIOS SE7500CW2 Server Board Technical Product Specification Table 31: Boot Menu Boot Priority Device Description Boot Device Removable Devices Specifies the boot sequence according to the device type. The computer will attempt to Boot Device Hard Drive boot from up to five devices as specified here...

  • Page 79: Exit Menu

    SE7500CW2 Server Board Technical Product Specification System BIOS Feature Choices Description <Enter> Provides basic information on the processor. Boot Strap Processor: Installed Speed: 1.8 GHz (for example) Socket Name: BSP Manufacturer: Genuine Intel Version: Intel(R) XEON(TM) CPUID: 3FEBFBFF00000F24 L2 Cache: 512KB Application Processor: Installed Speed: 1.8 GHZ (for example)
  • Page 80 System BIOS SE7500CW2 Server Board Technical Product Specification Choices Description Load Setup Defaults Loads default values for all Setup items. Discard Changes Reads a previous value of all Setup items from CMOS. Save Changes Writes all Setup item values to CMOS.

  • Page 81: Bios Security Features

    Note: The SE7500CW2 server board has the ability to boot from a device attached to the USB port, such as a floppy disk, disk drive or CD-ROM, or ZIP* drive, even if it is attached through a hub.
  • Page 82 System BIOS SE7500CW2 Server Board Technical Product Specification 6.6.2.1 Supervisor/User Passwords and F2 Setup Usage Model Note: 1. Visible = option string is active and changeable 2. Shaded = option string is grayed-out and view-only 6.6.2.1.1 Three Scenarios Scenario# 1...

  • Page 83: Error Reporting And Handling

    The error codes are defined by Intel and whenever possible are backward compatible with error codes used on earlier platforms.
  • Page 84 Error Reporting and Handling SE7500CW2 Server Board Technical Product Specification Tpoint Description Initialize external cache before auto-sizing memory. Initialize all three of the 8254 timers. Set the clock timer (0) to binary count, mode 3 (square wave mode), and read/write LSB then MSB. Initialize the clock timer to zero. Set the RAM refresh timer (1) to binary count, mode 2 (Rate Generator), and read/write LSB only.
  • Page 85 SE7500CW2 Server Board Technical Product Specification Error Reporting and Handling Tpoint Description POST tasks require interrupts off, preserve them with a PUSHF and CLI at the beginning and a POPF at the end. If you change the PIC, preserve the existing bits.
  • Page 86 Error Reporting and Handling SE7500CW2 Server Board Technical Product Specification Tpoint Description Count the number of ATA drives in the system and update the number in bdaFdiskcount. Initialize hard-disk controller. If the CMOS ram is valid and intact, and fixed disks are defined, call the fixed disk init routine to initialize the fixed disk system and take over the appropriate interrupt vectors.

  • Page 87: Table 36: Crisis Disk Boot Block Bios Post Task Point

    SE7500CW2 Server Board Technical Product Specification Error Reporting and Handling Tpoint Description Fade out OEM screen. Reset video: clear screen, reset cursor, reload DAC. ENDIF ENDIF If password on boot is enabled, a call is made to Setup to check password. If the user does not enter a valid password, Setup does not return.

  • Page 88: Bios Post Beep Codes

    The beep code occurs only when a critical error or BIOS fails to boot to the operating system. Please note that not all error conditions are supported by BIOS Beep codes. The following list contains some of the beep codes used in SE7500CW2 platform: •...

  • Page 89: Bios Recovery Beep Codes

    If your system displays one of the messages marked below with an asterisk (*), write down the message and contact Intel Customer Support. If your system fails after you make changes in the Setup menus, reset the computer, enter Setup and install Setup defaults or correct the error.
  • Page 90 Error Reporting and Handling SE7500CW2 Server Board Technical Product Specification System CMOS has been corrupted or modified incorrectly, perhaps by an application program that changes data stored in CMOS. The BIOS installed Default Setup Values. If you do not want these values, enter Setup and enter your own values. If the error persists, check the system battery or contact your dealer.
  • Page 91 SE7500CW2 Server Board Technical Product Specification Error Reporting and Handling Invalid System Configuration Data Problem with NVRAM (CMOS) data. IO device IRQ conflict I/O device IRQ conflict error. PS/2 Mouse Boot Summary Screen PS/2 Mouse installed. nnnnM Extended RAM Passed Where is the amount of RAM in megabytes successfully tested.

  • Page 92: Memory Error Codes

    Error Reporting and Handling SE7500CW2 Server Board Technical Product Specification 7.1.5 Memory Error Codes If memory errors occur the POST the user will see the following error codes and messages. Table 40: Memory Error Codes Tpoint Description 0E1h No memory DIMM(s)

  • Page 93: Se7500Cw2 Connectors And Jumper Blocks

    SE7500CW2 Server Board Technical Product Specification SE7500CW2 Connectors and Jumper Blocks Main Power Connector The main power supply connection is obtained using the 24-pin connector. The following table defines the pin-outs of the connector. Table 41. Power Connector Pin-out (J26)
  • Page 94 SE7500CW2 Connectors and Jumper BlocksSE7500CW2 Server Board Technical Product Specification +12VENG +12VENG Revision 1.40...

  • Page 95: Memory Module Connector

    SE7500CW2 Server Board Technical Product SpecificationSE7500CW2 Connectors and Jumper Blocks Memory Module Connector The SE7500CW2 server board has four DDR DIMM connectors and supports registered ECC DDR modules. Table 44. DIMM Connectors (J37, J38, J39, J40) Front Front Front Back...

  • Page 96: Processor Heat Syncs

    Pads Table 45: Processor Heat Sync data – replacement information Processor Socket The SE7500CW2 has two 604-pin processor sockets. The following table provides the processor socket pin numbers and pin names: Table 46. Socket 604 Processor Socket Pinout Pin No...
  • Page 97 SE7500CW2 Server Board Technical Product SpecificationSE7500CW2 Connectors and Jumper Blocks HITM# AB25 RS0# AB26 HIT# AB27 Reserved AB28 SM_EP_A2 AB29 SM_EP_A1 AB30 AB31 FERR# Reserved Reserved VID4 D60# D59# OTDEN VID0 D56# A31# D47# A27# BPM3# AC10 BPM0# AC11 D43#...
  • Page 98 SE7500CW2 Connectors and Jumper BlocksSE7500CW2 Server Board Technical Product Specification A30# AD13 D38# A23# DSTBP1# AD14 D39# LINT1 DSTBN1# AD15 A16# AD16 COMP0 A15# DSTBP0# AD17 DSTBN0# AD18 D36# AD19 D30# AD20 AD21 D29# REQ3# AD22 DBI1# REQ2# AD23 Reserved...

  • Page 99: System Management Headers

    +5VSB PCI Slot Connector There are three PCI buses implemented on the SE7500CW2 board. PCI segment A supports 5V 32-bit/33MHz PCI, segment B supports 3.3V PCI-X 64-bit/100MHz, and segment C supports 3.3V PCI-X 64-bit/133MHz operation. All segments supports full length PCI add-in cards. The pin- out for each segment is below.

  • Page 100: Table 49. P64-B/P64-C 3.3V 64-Bit/ 100Mhz/133Mhz Pci-X Slot Pin-Out

    SE7500CW2 Connectors and Jumper BlocksSE7500CW2 Server Board Technical Product Specification AD[29] +3.3V AD[08] C/BE[0]# Ground AD[28] AD[07] +3.3V AD[27] AD[26] +3.3V AD[06] AD[25] Ground AD[05] AD[04] +3.3V AD[24] AD[03] Ground C/BE[3]# IDSEL Ground AD[02] AD[23] +3.3V AD[01] AD[00] Ground AD[22]...

  • Page 101: Front Panel Connectors

    SE7500CW2 Server Board Technical Product SpecificationSE7500CW2 Connectors and Jumper Blocks Ground FRAME# AD[47] AD[46] IRDY# Ground AD[45] Ground +3.3V TRDY# Ground AD[44] DEVSEL# Ground AD[43] AD[42] PCIXCAP STOP# AD[41] +3.3V (I/O) LOCK# +3.3V Ground AD[40] PERR# SMBCLK AD[39] AD[38] +3.3V...

  • Page 102: Nic Connectors

    DDCDAT HSYNC (horizontal sync) VSYNC (vertical sync) DDCCLK NIC Connectors The SE7500CW2 server board supports two NIC RJ45 connectors. The following table details the pin-out of the connector. Table 52. RJ-45 Connector Pin-outs (J47) Signal Name Signal Name TXP (Primary)

  • Page 103: 8.11 Usb Connector

    SE7500CW2 Server Board Technical Product SpecificationSE7500CW2 Connectors and Jumper Blocks Table 53. ATA-100 40-pin Connectors Pin-out (J4, J5, J6, J7) Signal Name Signal Name RESET_L IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15 IDE_DMAREQ IDE_IOW_L IDE_IOR_L IDE_IORDY IDE_DMAACK_L IRQ_IDE Test Point...

  • Page 104: 8.12 Floppy Connector

    Front Panel USB Overcurrent signal (Ports 0,1). This signal is not used 8.12 Floppy Connector The SE7500CW2 server board provides a standard 34-pin interface to the floppy drive controller. The following tables detail the pin-out of the 34-pin legacy floppy connector.

  • Page 105: 8.13 Serial Port Connectors

    SE7500CW2 Server Board Technical Product SpecificationSE7500CW2 Connectors and Jumper Blocks 8.13 Serial Port Connectors Two serial ports are provided on the server board. • A standard, external DB9 serial connector is located on the back edge of the baseboard to supply a Serial 1 interface •...

  • Page 106: 8.14 Keyboard And Mouse Connector

    8.15 Miscellaneous Headers and Jumpers 8.15.1 Fan Headers The SE7500CW2 server board provides six 3-pin fan headers. All fans provide variable speed control. The fan headers are labeled, CPU Fan 1, CPU Fan 2, SysFan 1, SysFan 2, SysFan 3, SysFan 4.

  • Page 107: System Recovery And Update Jumpers

    SE7500CW2 Server Board Technical Product SpecificationSE7500CW2 Connectors and Jumper Blocks 8.15.2 System Recovery and Update Jumpers One 8-pin header (J106), located near the NIC 1 connector, provides a total of five 2-pin jumper blocks that are used to configure several system recovery and update options. The figure below shows the jumper pins and their functions.

  • Page 108: General Specifications

    The following table shows the power consumed on each supply line for a Intel Server Board SE7500CW2 that is configured with two processors (each 30W max), >1GHz FMB @ 75% usage. This configuration includes four DIMMs stacked burst at 70% max. The numbers provided in the table should be used for reference purposes only.

  • Page 109: Table 63. Intel® Server Board Se7500Cw2 Power Budget

    SE7500CW2 Server Board Technical Product Specification General Specifications Table 63. Intel® Server Board SE7500CW2 Power Budget Items Output Max Current (V) Output Average Current (V) Utilize Average Mother Board Q'ty Power factor power +3.3 -12 -5 +3.3 -12 -5 Processor Vcore 178.49...

  • Page 110: Mean Time Between Failures (Mtbf) Test Results

    DDR Vtt 6.2A Mean Time Between Failures (MTBF) Test Results This section provides results of MTBF as supplied by non-Intel testing. MTBF is a common server board testing that validates server boards for reliability and performance under extreme working conditions. Time between failures was measured at 108,621 hours when tested at 40 degrees Centigrade.

  • Page 111: Power Supply Specifications

    SE7500CW2 Server Board Technical Product Specification General Specifications Power Supply Specifications ® This section provides power supply design guidelines for an Intel Server Board SE7500CW2- based system, including voltage and current specifications, and power supply on/off sequencing characteristics. Table 64. SE7500CW2 Static Power Supply Voltage Specification...

  • Page 112: Figure 10. Output Voltage Timing

    General Specifications SE7500CW2 Server Board Technical Product Specification Vout Vout vout_rise vout_off vout_on Figure 10. Output Voltage Timing The following tables show the timing requirements for a single power supply being turned on and off via the AC input, with PSON held low and the PSON signal, with the AC input applied. The ACOK# signal is not being used to enable the turn on timing of the power supply.

  • Page 113: Figure 11. Turn On / Off Timing

    SE7500CW2 Server Board Technical Product Specification General Specifications AC Input vout_holdup Vout pwok_low AC_on_delay pwok_off sb_on_delay sb_on_delay pwok_on pwok_off pwok_on PWOK pson_pwok pwok_holdup 5VSB sb_vout pson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 11. Turn on / off Timing Table 67.

  • Page 114: Voltage Recovery Timing Specifications

    Shock and vibe testing is a rigorous set of tests which test board strength and durability under extreme conditions. The SE7500CW2 board has been tested in the SC5200 Base chassis with the 450W power-supply and the results are as follows: •...

  • Page 115: 10. Product Regulatory Compliance

    10.1.2 Product EMC Compliance The SE7500CW2 has been has been tested and verified to comply with the following electromagnetic compatibility (EMC) regulations when installed in a compatible Intel host system. For information on compatible host system(s), contact your local Intel representative.

  • Page 116: Product Regulatory Compliance Markings

    Product Regulatory Compliance SE7500CW2 Server Board Technical Product Specification 10.1.3 Product Regulatory Compliance Markings This product is provided with the following product certification markings: • cURus Recognition Mark • CE Mark • Russian GOST Mark • Australian C-Tick Mark •...

  • Page 117: 10.3 Replacing The Back-Up Battery

    SE7500CW2 Server Board Technical Product Specification Product Regulatory Compliance 10.3 Replacing the Back-Up Battery The lithium battery on the server board powers the RTC for up to 10 years in the absence of power. When the battery starts to weaken, it loses voltage, and the server settings stored in CMOS RAM in the RTC (for example, the date and time) may be wrong.

  • Page 118: 11. Mechanical Spefications

    Mechanical Spefications SE7500CW2 Server Board Technical Product Specification 11. Mechanical Spefications 11.1 Mechanical Specifications The following figure shows the server board mechanical drawing. Figure 12. SE7500CW2 Server Board Mechanical Drawing Revision 1.40...
  • Page 119 SE7500CW2 Server Board Technical Product Specification Mechanical Spefications Table 69. Server Board Connector Specifications Item Q'ty Manufacturer and Part Number Description AMP 1489688-1 604P Socket 603/604 Lotes F1366RB5L 3P CPU Fan 1 Lotes F1366RB5L 3P CPU Fan 2 Lotes F1366RB5L...
  • Page 120 Mechanical Spefications SE7500CW2 Server Board Technical Product Specification < This page intentionally left blank. > Revision 1.40...

  • Page 121: Appendix A: Se7500Cw2 Integration And Usage Tips

    Appendix A: SE7500CW2 Integration and Usage Tips Appendix A: SE7500CW2 Integration and Usage Tips This section provides a bullet list of useful information that is unique to the SE7500CW2 server board and should be kept in mind while assembling and configuring your SE7500CW2 based server.
  • Page 122 Appendix A: SE7500CW2 Integration and Usage Tips SE7500CW2 Server Board Technical Product Specification Revision 1.40...

  • Page 123: Appendix B: Se7500Cw2Errata Documentation

    Appendix B: SE7500CW2Errata documentation Table 70. Errata Summary Plans Description of Errata Fixed Intel® Xeon processors 2.6 GHz and 2.8 GHz C1 stepping not supported in BIOS 1.14. Fixed LDCM 6.3 reported processor speeds change after a system reboot. Fixed I can’t get my Adaptec 2100S RAID card to clear POST.

  • Page 124: 12. Errata

    Use the processor speed listed in BIOS <F2> setup under the “System – CPU” sub-menu. Status Intel is investigating the possiblity of fixing this erratum. My SE7500CW2 system won’t boot to DOS with an Adaptec* card installed. Problem SE7500CW2 system boots to the Adaptec SMOR utility instead of booting into CXII Revision 1.40...
  • Page 125 This issue is resolved with a new release of the Adaptec BIOS and SE7500CW2 BIOS 1.16. The Adaptec BIOS v1.30 should work correctly. BIOS 1.16 and 1.17 are now available for the SE7500CW2. Both should work properly with this card.

  • Page 126: Status Intel Is Investigating The Possibility Of Fixing This Erratum

    CDROM. Both devices will be displayed as a “CD-ROM Drive” under <F2> setup “BOOT” sub-menu. Implication If you concurrently install an IDE and an USB CD-ROM on SE7500CW2 you will be unable to determine which device is first in the boot-order in BIOS 1.17 and below.
  • Page 127 LDCM 6.3 build 211 incorrectly lowers processor fan speeds from 6000 RPM to fewer than 2000 RPM. Problem LDCM 6.3 build 211 incorrectly lowers fan speeds on the SE7500CW2 system only. Implication Installing and configuring LDCM 6.3 build 211 could possibly create thermal overheating issues.
  • Page 128 Performance Clusters (HPC) to work properly. Implication The only way to uniquely identify a SE7500CW2 system board is by reading the bar code number sticker next to the Onboard Promise* RAID chip (PDC20267). An example of the unique identifier would be BPCW23701091.
  • Page 129 Logical processors are not listed in BIOS 1.18 and above even if hyper- threading is enabled in BIOS. Logical processrs are no longer mentioned with the text string of “4 Logical Intel® Xeon™ 2.8 Ghz processors” if hyper- threading is enabled with two processors populated.

  • Page 130: Glossary

    Glossary SE7500CW2 Server Board Technical Product Specification Glossary Term Definition ACPI Advanced Configuration and Power Interface ANSI American National Standards Institute Application Processor ASIC Application Specific Integrated Circuit Asynchronous Reset Ball-grid Array BIOS Basic input/output system BIST Built-in self test Bridge Circuitry connecting one computer bus to another, allowing an agent on one to access the other.
  • Page 131 SE7500CW2 Server Board Technical Product Specification Glossary Term Definition IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface Interrupt Request ® Intel Server Control In-target probe 1024 bytes Keyboard Controller Style Local area network Logical Block Address Liquid crystal display...
  • Page 132 Glossary SE7500CW2 Server Board Technical Product Specification Term Definition RISC Reduced instruction set computing RMCP Remote Management Control Protocol Read Only Memory Real Time Clock SAF-TE SCSI Accessed Fault-Tolerant Enclosure Specification Single-Bit Error System Configuration Interrupt Sensor Data Record SDRAM...

  • Page 133: Reference Documents

    SE7500CW2 BIOS External Product Specification rev 1.0 • SE7500CW2 Baseboard External Product Specification 1.0 • Windbond** 83627HF Super I/O Controller Technical Reference, rev 1.0 (www.Windbond*.com) Please contact your Intel field person for informaiton on how to obtain this document. Revision 1.40 CXXI...

  • Page 134: Index

    Index SE7500CW2 Server Board Technical Product Specification Index BMC, 89 Boot device, 35 Bridge, CIV BSP, CIV Built-in Self Test 28F320C3, 15 See also BIST, CIV 2-way interleave, 29, 30 Built-in Self Test, See also BIST, CIV 2-way interleaving, 29...
  • Page 135 IMB, CIV , 2, 4, 6, 7, 9, 79, CIV IMB bus, 9, 11 EEPROM, 29 Intel Server Control, See also ISC v2.x, See also ISC Emergency management port, 37, 39 v3.x, CIV Emergency Management Port, See also EMP, CIV...
  • Page 136 Index SE7500CW2 Server Board Technical Product Specification MCH, 9 Power button, 36, 37, 38 MDI, 19 Power Distribution Board, 78, CV Mean Time Between Failures, 100, CV Power management, 12 Memory, 6, 18, CIII, CIV, CV power management controller, 12, 14...
  • Page 137 SDRAM, 2, 4, 7, 9, 17, 28, 79, CVI System Management Mode, CVI SE75000CW2SE7500CW2, 1 System Management Software, CVI SE7500CW2, 1, iii, 19, 78, 87, 89, 91, 97, 100, CIII System Setup Utility, 33 Secure mode, 68 Security, 47 Sensor Event, CV...
  • Page 138 Index SE7500CW2 Server Board Technical Product Specification Xeon® Processor, iii Xeon® Processor, CIII CXXVI Revision 1.40...

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