Processor Bus; Zx1 I/O And Memory Controller; Memory - HP Rx2620-2 - Integrity - 0 MB RAM Service Manual

The front side bus (FSB) is the IA64 processor bus, based on bus protocol from Intel. Unlike
previous PA-RISC microprocessors that utilized HP proprietary processor buses, this processor
is designed to utilize the FSB. This allows processor field replaceable units (FRUs) to be dropped
in, provided that electrical and mechanical compatibility and support circuitry exist. For the
purposes of this document, a FRU consists of a single processor with power pod, and the heat
sink assembly.
Each processor plugs directly into, and is powered by its own 12 V to 1.2 V power pod. Other
power for the system board comes from multiple on-board DC to DC converters. Each processor
is attached to the board through a ZIF socket and the entire FRU secured by a heat sink.

Processor Bus

The FSB in this product runs at 200 MHz. Data on the FSB are transferred at a double data rate,
which allows a peak FSB bandwidth of 6.4 Gb/s.

ZX1 I/O and Memory Controller

The server supports the following features of the ZX1 I/O and memory controller chip:
• 8.5 Gb/s peak I/O bandwidth
• Seven communication paths
• Peak memory bandwidth of 8.5 Gb/s
• Two memory cells, 144 data bits each

Memory

The memory subsystem provides two memory cells. Each cell is 144 data bits wide. Each cell has
six DIMM slots, which means a total of 12 DIMM slots are available. The memory bus clock speed
is 133 MHz, and the data transfer rate is 266 Mtransfers/s as data is clocked on both edges of the
clock. The peak data bandwidth for this memory subsystem design is 8.5 Gb/s. Load DIMMs in
quads with qualified modules. Memory is protected by data ECC, and the hardware
implementation supports chip-spare.
The minimum amount of memory supported by the server is 1 GB (four 256 MB modules). The
maximum amount of memory supported by the server is 32 GB (eight 4 GB modules).
This design does not support any nonindustry-standard DDR DIMMs. Only qualified DIMMs
are supported. Figure 1-5 shows a block diagram of the server memory.
System Board Components 23