Intel Itanium 2 Processor; Processor Bus; I/O And Memory Controller; Memory Architecture - HP Integrity rx1600 Operation And Maintenance Manual

System Information
System Board
• SCSI Controller
• IDE Controller
• USB Controller
• 10/100BT Standard/Management LAN
• 10/100/1000 LAN

Intel Itanium 2 Processor

The Intel Itanium 2 processor provides the following features:
• Eight-stage pipeline, six general-purpose ALUs, two integer units, one shift unit, four floating-point units
• Split L1 cache:
— 16 KB, 4-way set associative data cache
— 16 KB, 4-way set associative instruction cache
— 64 byte line size
• Unified L2 cache:
— 256 KB, 8-way set associative
— 128 byte line size
• Unified L3 cache:
— 3MB, 12-way set associative (1 GHz)
— 1.5 MB, 6-way set associative (900 MHz)
— 128 byte line size

Processor Bus

The processor bus (Front Side Bus, FSB) in this product runs at 200 MHz. Data on the FSB are transferred at a double data
rate, which allows a peak FSB bandwidth of 6.4 GB/sec.

I/O and Memory Controller

The hp Integrity rx1600 Server supports the following features of the I/O and memory controller chip:
• 3.3 GB/s peak IO bandwidth.
• provides 7 communication paths.
• Peak memory bandwidth of 8.5 GB/s.
• 2 memory cells, 144 data bits each.

Memory Architecture

The memory subsystem includes the memory controller and the DDR SDRAM memory DIMMs, along with the memory bus
traces and required termination. The memory subsystem provides two memory cells, 144 bits wide each (128 bits of data, 16
bits of ECC). Each cell can accommodate up to 6 DIMM slots; however, in Nemesis, power limitations restrict the total loaded
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Appendix A