STC8A8K64D4 Series Manual
ELVD
BIT
LVDF
EQU
P0M1
DATA
P0M0
DATA
P1M1
DATA
P1M0
DATA
P2M1
DATA
P2M0
DATA
P3M1
DATA
P3M0
DATA
P4M1
DATA
P4M0
DATA
P5M1
DATA
P5M0
DATA
ORG
LJMP
ORG
LJMP
ORG
LVDISR:
ANL
CPL
RETI
MAIN:
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
;
MOV
MOV
SETB
SETB
JMP
END
6.7.6 Power Saving Mode
C language code
// Operating frequency for test is 11.0592MHz
#include "reg51.h"
#include "intrins.h"
#define
IDL
IE.6
20H
093H
094H
091H
092H
095H
096H
0B1H
0B2H
0B3H
0B4H
0C9H
0CAH
0000H
MAIN
0033H
LVDISR
0100H
PCON,#NOT LVDF
P3.2
SP, #5FH
P0M0, #00H
P0M1, #00H
P1M0, #00H
P1M1, #00H
P2M0, #00H
P2M1, #00H
P3M0, #00H
P3M1, #00H
P4M0, #00H
P4M1, #00H
P5M0, #00H
P5M1, #00H
PCON,#NOT LVDF
RSTCFG,#ENLVR | LVD3V0
RSTCFG,#LVD3V0
ELVD
EA
$
0x01
;PCON.5
;Clear interrupt flag
;Test port
;LVDF flag needs to be cleared after power on
;Low voltage reset when 3.0V is enabled, no LVD interrupt is generated
;Low voltage interrupt when 3.0V is enabled
;Enable LVD interrupt
//PCON.0
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