Pwm Interrupt Flag Register (Pwmif); Pwm Fault Detection Control Register (Pwmfdcr) - STC micro STC8A8K64D4 Series Reference Manual

STC8A8K64D4 Series Manual
0: disable PWM counter returns to zero interrupt (PWMCBIF is still set by hardware)
1: enable PWM counter returns to zero interrupt
EPWMTA: Whether the PWM is associated with the ADC or not.
0: PWM is not associated with the ADC.
1: PWM is associated with the ADC. A/D conversion is enabled to be triggered at a certain point in the PWM
cycle. PWMTADCH and PWMTADCL are used to set the counter value..
(Note: The ADC_POWER and ADC_EPWMT bits in the ADC_CONTR register need to be set at the same
time to enable the PWM triger function. PWM only sets ADC_START to 1
PWMCEN: PWMn waveform generator starts counting control bit.
0: PWM stops counting
1: PWM starts counting
Important note about the PWMCEN control bit:
⚫ Once PWMCEN is enabled, the internal PWM counter will start counting immediately and compare the
counting value with the value of T1/T2. So PWMCEN must be enabled after all other PWM settings (including
T1 / T2 settings, initial level setting, PWM fault detection setting and PWM interrupt setting) are completed.
⚫ During the PWM counter counting, when the PWMCEN control bit is turned off, the PWM counting will stop
immediately. When the PWMCEN control bit is enabled again, the PWM counting will start counting from 0
again without remembering the count value before the PWM stopped counting.
⚫ Special attention: When PWMCEN changes from 0 to 1, the internal PWM counter starts to count again after
returning to zero from the previous uncertain value, so a reset interrupt will be generated immediately at this
time. When the user needs to use the reset to zero interrupt of PWM, special attention should be paid to this
point, that is, the first reset to zero interrupt is not generated by the reset to zero after the real PWM cycle is
full.

19.2.3 PWM Interrupt Flag Register (PWMIF)

Symbol Address
PWMIF FF05H
CiIF: The interrupt flag bit of i-channel of PWM. (i＝0~7)
T1 and T2 of each PWM can be set. When a match event occurs at the set point, this bit is set by hardware
automatically and an interrupt is requested to the CPU. This flag bit must be cleared by software.

19.2.4 PWM Fault Detection Control Register (PWMFDCR)

Symbol Address
PWMFDCR FF06H
INVCMP: Fault signal of comparator result selection bit
0: the fault signal is the comparator result changing from low to high.
1: the fault signal is the comparator result changing from high to low.
INVIO: Fault signal of external port PWMFLT selection bit
0: the fault signal is the external port PWMFLT signal changing from low to high.
1: the fault signal is the external port PWMFLT signal changing from high to low.
ENFD: PWM external fault detection enable bit.
0: disable the PWM external fault detection.
1: enable the PWM external fault detection.
FLTFLIO: PWM output port control bit when external PWM fault occurs.
0: the PWM output port does not change when external PWM fault occurs.
1: the PWM outport port is set as high impedance input mode when external PWM default occurs.
Note: Only the port whose corresponding ENO = 1 is forcibly in high impedance state.
EFDI: PWM fault detection interrupt enable bit.
0: disable PWM fault detection interrupt (FDIF will still be set by hardware.)
1: enable PWM fault detection interrupt
FDCMP: fault detection of comparator output enable bit.
0: the comparator is not associated with PWM.
1: the source of PWM fault detection is comparator output. (The fault type is set by INVCMP.)
FDIO: PWMFLT level fault detection enable bit.
B7 B6
C7IF C6IF C5IF
B7 B6 B5
INVCMP INVIO ENFD
B5 B4 B3
C4IF C3IF
B4 B3
FLTFLIO EFDI
automatically.)
B2 B1 B0
C2IF C1IF C0IF
B2 B1 B0
FDCMP FDIO FDIF
- 546 -