Uart1; Uart1 Control Register; Uart1 Data Register - STC micro STC8A8K64D4 Series Reference Manual

STC8A8K64D4 Series Manual

14.3 UART1

14.3.1 UART1 control register

Symbol Address
SCON 98H
SM0/FE: If the SMOD0 bit in the PCON register is 1, this bit is the frame error detection flag. When the UART detects
an invalid stop bit during reception, it is set by the UART receiver and must be cleared by software. If SMOD0
bit in PCON register is 0, this bit and SM1 specify the communication mode of UART1 as shown in the following
table:
SM0 SM1 Mode of UART1
0 0 Mode 0
0 1 Mode 1
1 0 Mode 2
1 1 Mode 3
SM2: Mode 2 or mode 3 multi-machine communication enable control bit. When UART1 adopts mode 2 or mode 3, if
the SM2 bit is 1 and the REN bit is 1, the receiver is in the Address Frame Filter state. In this case, the received
9th bit (RB8) can be used to filter the address frame. If RB8 = 1, it indicates that the frame is an address frame,
the address information can enter SBUF and set RI bit. The address information is compared in the interrupt
service routine. If RB8 = 0, it indicates that the frame is not an address frame, which should be discarded and
keep RI = 0. In mode 2 or mode 3, if the SM2 bit is 0 and the REN bit is 1, the receiver is in a state where the
address frame filtering is disabled. The received message can enter SBUF regardless of whether RB8 is 0 or 1,
and make RI = 1. Here, RB8 is usually used as a check bit. Mode 1 and mode 0 are non-multi-machine
communication modes. In these two modes, SM2 should be set to 0.
REN: Receive enable control bit.
0: disable UART1 receive data.
1: enable UART1 receive data.
TB8: The 9th bit be transmitted for UART1 in mode 2 and 3. It can be set or cleared by software. It is not used in mode
0 and mode 1.
RB8: The 9th bit received for UART1 in mode 2 and 3 which is usually used as a check bit or address frame/data frame
flag. It is not used in mode 0 and mode 1.
TI: Transmit interrupt request flag of UART1. In mode 0, when the ransmission of the 8th bit completes, TI is set by
the hardware automatically and requests the interrupt to the CPU. After the CPU responds the interrupt, TI must
be cleared by software. In other modes, TI is set by the hardware automatically at the start of the stop bit
transmittion and requests interrupts to the CPU. TI must be cleared by software after the interrupt is responded.
RI: Receive interrupt request flag of UART1. In mode 0, when the serial port receives the 8th bit of datum, RI is set by
the hardware automatically and requests interrupt to the CPU. After the interrupt is responded, RI must be
cleared by software. In other modes, RI is set by hardware automatically at the middle of stop bit the serial port
received, and requests the interrupt to the CPU. After the interrupt is responded, RI must be cleared by software.

14.3.2 UART1 data register

Symbol Address
SBUF 99H
SBUF: It is used as the buffer in transmission and receiving of UART1. SBUF is actually two buffers, reading buffer
and writing buffer. Two operations correspond to two different registers, one is write-only register (writing
buffer), the other is read-only register (reading buffer). In fact, the CPU reads serial receive buffer when reads
SBUF. When CPU writes to the SBUF will trigger the serial port to start sending data.
B7 B6
SM0/FE SM1
Function description
synchronous shift serial mode
8-bit UART, whose baud-rate is variable
9-bit UART, whose baud-rate is fixed
9-bit UART, whose baud-rate is variable
B7 B6
B5 B4 B3
SM2 REN TB8
B5 B4 B3
B2 B1 B0
RB8 TI RI
B2 B1 B0
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