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STC STC12C5A Series Manual

8-bit micro-controller
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Features ............................................................................................................................. 3 
General Description .......................................................................................................... 4 
Order Information: ............................................................................................................ 4 
Pin Description .................................................................................................................. 5 
Pin Definition ............................................................................................................ 5 
Pin Configuration ...................................................................................................... 7 
Block Diagram .................................................................................................................. 9 
Address Map ........................................................................................................... 10 
Bits Description ...................................................................................................... 11 
Memory ........................................................................................................................... 13 
Organization ............................................................................................................ 13 
RAM ....................................................................................................................... 13 
Embedded Flash ...................................................................................................... 14 
ALE OUTPUT ................................................................................................................ 15 
Functional Description .................................................................................................... 17 
I/O Port Configuration ............................................................................................ 17 
Timer/Counter ......................................................................................................... 21 
BAUD-RATE GENERATOR(BRT) ....................................................................... 25 
Interrupt ................................................................................................................... 27 
Watch Dog Timer .................................................................................................... 34 
Universal Asynchronous Serial Port (UART) ......................................................... 36 
Secondary Universal Asynchronous Serial Port (S2) ............................................. 40 
Programmable Counter Array (PCA) ...................................................................... 45 
Serial Peripheral Interface(SPI) .............................................................................. 55 
Analog to Digital Converter .................................................................................... 63 
Power Management ................................................................................................ 66 
In System Programming and In Application Programming .................................... 69 
In System Programming (ISP) ................................................................................ 69 
In-Application Program (IAP) ................................................................................ 72 
Instructions Set ................................................................................................................ 72 
Absolute Maximum Rating (STC12C5Axx) .................................................................. 75 
DC Characteristics (STC12C5Axx) ................................................................................ 75 
Absolute Maximum Rating (STC12LE5Axx) ................................................................ 76 
DC Characteristics (STC12LE5Axx) ............................................................................. 76 
Package Dimension ......................................................................................................... 77 
This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this
product without notice.
STC TECHNOLOGY Co.,Ltd.
http://www.DataSheet4U.net/
STC12C5A08/16/32/60
8-bit micro-controller
2007/12 version A1
datasheet pdf - http://www.DataSheet4U.net/

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Summary of Contents for STC STC12C5A Series

  • Page 1: Table Of Contents

    Absolute Maximum Rating (STC12LE5Axx) ..............76  DC Characteristics (STC12LE5Axx) ................76  Package Dimension ......................77  This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1...
  • Page 2 Version History ....................... 78  http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...

  • Page 3: Features

    Features Enhanced 80C51 Central Processing Unit 3.3V/5V operation voltage, built-in Low-Voltage Detector and Reset circuit Operation frequency range up to 25MHz Max 64K bytes on-chip flash memory with ISP/IAP capability 256 byte scratch-pad RAM and 1024 bytes of auxiliary RAM Two-level code protection for flash memory access Two 16-bit timer/counter 10 sources, 4-level-priority interrupt capability...

  • Page 4: General Description

    General Description STC12C5Axx is a single-chip 8-bit micro-controller with instruction sets fully compatible with industrial-standard 80C51 series micro controller. There is very excellent MCU kernel built in this device compared to general 80C51 MCUs those take twelve oscillating cycles to finish an instruction, the device could take only one oscillating cycle to finish one instruction.

  • Page 5: Pin Description

    Pin Description Pin Definition Package Type MNEMONIC DESCRIPTION PDIP40 PLCC44 PQFP44 LQFP48 P0.0 ~ P0.7 32-39 43-34 37-30 40-33 Port0 open-drain, Port0: bi-directional IO port. When 1s are written Port0, they become high-impedance inputs. Port0 is also the multiplexed low-order address and data bus during accesses to external program and data memory.
  • Page 6 P4.0/SS Port4: Port4 are extended I/O ports P4.1/ECI/MOSI such like Port1. It can be available P4.2/CCP0/MISO only on 44L-PLCC, 44L-PQFP and P4.3/CCP1/SCLK 48L-LQFP. P4.4/NA P4.5/ALE ALE: Address Latch P4.6/EX_LVD/RST2 EX_LVD: External Low Voltage Reset P4.7/RST Detector. RESET RESET: A high on this pin for at least two machine cycles will reset the device.

  • Page 7: Pin Configuration

    Pin Configuration CLKOUT2/P1.0 P1.1 P0.0/AD0 ECI/P1.2 P0.1/AD1 P0.2/AD2 CCP0/P1.3 P0.3/AD3 SS/CCP1/P1.4 P0.4/AD4 MOSI/P1.5 P0.5/AD5 MISO/P1.6 P0.6/AD6 SCLK/P1.7 P0.7/AD7 RST/P4.7 STC12C5Axx RXD/P3.0 EX_LVD/P4.6/RST2 TXD/P3.1 ALE/P4.5 PDIP-40 INT0/P3.2 NA/P4.4 INT1/P3.3 P2.7/A15 CLKOUT0/T0/P3.4 P2.6/A14 CLKOUT1/T1/P3.5 P2.5/A13 WR/P3.6 P2.4/A12 P2.3/A11 RD/P3.7 P2.2/A10 XTAL2 XTAL1 P2.1/A9 P2.0/A8 http://www.DataSheet4U.net/...
  • Page 8 P4.5/ALE TXD/P3.1 NA/P4.4 INT0/P3.2 P2.7/A15 INT1/P3.3 P2.6/A14 CLKOUT0/T0/P3.4 P2.5/A13 CLKOUT1/T1/P3.5 This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1 datasheet pdf - http://www.DataSheet4U.net/...

  • Page 9: Block Diagram

    Block Diagram http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...

  • Page 10: Address Map

    Special Function Register Address Map CCAP0H CCAP1H PCAPWM0 PCAPWM1 CCAP0L CCAP1L CCON CMOD CCAPM0 CCAPM1 P5M1 P5M0 SPSTAT SPCTL SPDAT WDT_CONTR IAP_DATA IAP_ADDRH IAP_ADDRL IAP_CMD IAP_TRIG IAP_CONTR SADEN P4SW ADC_CONTR ADC_RES ADC_RESL P3M1 P3M0 P4M1 P4M0 IP2H IPHIPH SADDR BUS_SPEED AUXR1 TEST_WDT SCON...

  • Page 11: Bits Description

    Bits Description SYMBOL ADDRESS BIT ADDRESS AND SYMBOL INITIAL VALUE xxxx1111B 00000111B 00000000B 00000000B PCON xxxxxx00B TCON 00000000B TMOD GATE GATE 00000000B 00000000B 00000000B 00000000B 00000000B AUXR T0X12 T1X12 UART_ BRTR S2SMOD BRTX12 EXTRAM S1BRS 00xxxxxxB WAKE_CLKO RXD_PIN_ T1_PIN_ T0_PIN_ LVD_WA BRTCLK T1CLKO T0CLKO 00000x00B P1.7 P1.6...
  • Page 12 SADEN 00000000B P4SW LVD_P4.6 ALE_P4.5 NA/P4.4 x000xxxxB ADC_CONTR SPEED1 SPEED0 ADC_ ADC_ CHS2 CHS1 CHS0 00000000B ADC_RES 00000000B ADC_RESL 00000000B 11111111B WDT_CONTR WDT_ EN_WDT CLR_ IDL_ xx000000B IAP_DATA 11111111B IAP_ADDRESS 00000000B IAP ADDRESS 00000000B IAP CMD xxxxxx00B IAP_TRIG xxxxxxxxB IAP_CONTR IAPEN SWBS SWRST...

  • Page 13: Memory

    STC12C5Axx switches to access external RAM automatically. When EXTRAM=0, the content in DPH is ignored when the instruction MOVX @Ri is executed. This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice.

  • Page 14: Embedded Flash

    Embedded Flash There is totally 64K byte flash embedded in the STC12C5Axx. The user can configure the whole flash to store his application program, or he can configure the flash for both storage of application (AP) program and In-System-Program (ISP) code, even he can configure the flash for storage of AP, ISP, and In-Application-Program (IAP) memory.

  • Page 15: Ale Output

    001: 1 clock stretched, the MOVX read/write pulse is 2 clock cycles. 010: 2 clocks stretched, the MOVX read/write pulse is 3 clock cycles. This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice.
  • Page 16 011: 3 clocks stretched, the MOVX read/write pulse is 4 clock cycles. 100: 4 clocks stretched, the MOVX read/write pulse is 5 clock cycles. 101: 5 clocks stretched, the MOVX read/write pulse is 6 clock cycles. 110: 6 clocks stretched, the MOVX read/write pulse is 7 clock cycles. 111: 7 clocks stretched, the MOVX read/write pulse is 8 clock cycles.

  • Page 17: Functional Description

    Functional Description I/O Port Configuration There are 44(max) port pins on STC12C5Axx may be independently configured to one of four modes: quasi-bidirectional(standard 8051 port output), push-pull output, open-drain output or input-only. All port pins default to quasi-bidirectional after reset. Each port pin has a Schmitt-triggered input for improved input noise rejection.
  • Page 18 SFR: P3M1(P3 Configuration 1) Read/Write Address: 0XB1H Default: 0000-0000 Name P3M1.7 P3M1,6 P3M1.5 P3M1.4 P3M1.3 P3M1.2 P3M1.1 P3M1.0 SFR: P4M0(P4 Configuration 0) Read/Write Address: 0XB4H Default: 0000-0000 Name P4M0.7 P4M0,6 P4M0.5 P4M0.4 P4M0.3 P4M0.2 P4M0.1 P4M0.0 SFR: P4M1(P4 Configuration 1) Read/Write Address: 0XB3H Default: 0000-0000...
  • Page 19 Quasi-bidirectional Mode Port pins in quasi-bidirectional output mode function similar to the standard 8051 port pins. A quasi-bidirectional port can be used as an input and output without the need to reconfigure the port. This is possible because when the port outputs logic high, it is weakly driven, allowing an external device to pull the pin low.
  • Page 20 Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port register contains logic “0”. To use this configuration in application, a port pin must have an external pull-up, typically tied to VDD. The input path of the port pin in this configuration is the same as quasi-bidirection mode.

  • Page 21: Timer/Counter

    Timer/Counter STC12C5Axx has two 16-bit timers, and they are named T0 and T1. Each of them can also be used as a general event counter, which counts the transition from 1 to 0. Since the STC12C5Axx is a RISC-like MCU which execute faster than traditional 80C51 MCU from other providers.
  • Page 22 SFR: TCON Read/Write Address: 0X88H Default: 0000-0000 Name IE01 TF1: = Timer1 overflow flag. This bit is automatically set by hardware on T1 overflow, and will be automatically cleared by hardware when the processor vectors to the interrupt routine. TR1: = Timer1 run control bit. 0: = (default) Stop T1 counting 1: =...
  • Page 23 SFR: AUXR (Auxiliary Register) Read/Write Address: 0x8EH Default: 00XX-XXXX T0X12 T1X12 UARTM0X6 BRTR S2SMOD BRTRX12 EXTRAM S1BRS Name T0X12: = T0 clock source selector 0: = (default) Set the frequency of the clock source for T0 as the oscillator frequency divided-by-12. It will compatible to the traditional 80C51 MCU.
  • Page 24 Mode 0 The timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TFx. The counted input is enabled to the timer when TRx = 1 and either GATE=0 or INTx = 1.

  • Page 25: Baud-Rate Generator(Brt)

    Mode 3 Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0 and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such like C/T, GATE, TR0, INT0 and TF0. TH0 is locked into a timer function (can not be external event counter) and take over the use of TR1, TF1 from Timer1.
  • Page 26 STC12C5Axx is able to generate a programmable clock output on P1.0 or P4.1. When BRTCLKO bit in WAKE_CLKO is set, BRT timer overflow pulse will toggle P1.0 or P4.1 latch to generate a 50% duty clock. The frequency of clock-out is as following : osc/12 BRT timer overflow rate 256 –...

  • Page 27: Interrupt

    Interrupt There are 10 interrupt sources available in STC12C5Axx. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a global disable bit (EA), which can be cleared to disable all interrupts at once. Each interrupt source has two corresponding bits to represent its priority.
  • Page 28 The PCA interrupt is generated by the logical OR of CF, CCF0 ~ CCF1. The service routine should poll CF and CCF0 ~ CCF1 to determine which one to request service and it will be cleared by software. The Low Voltage Detect interrupt is shared by the flag LVDF in PCON.5 register. They should be cleared by software.
  • Page 29 F1 : = Flag 1. User-defined flag. Parity flag. This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1 d a t a s h e e t p d f - h t t p : / / w w w . D a t a S h e e t 4 U . n e t /...
  • Page 30 SFR: IE(Interrupt Enable) Read/Write Address: 0XA8H Default: XXXX-XX00 Name ELVD EADC Global interrupt controller. 0: = (default) Disable all interrupts 1: = Release interrupt control to all individual interrupt controllers. Interrupt controller of Low-Voltage Detector ELVD 0: = (default) Disable 1: = Enable EADC: = Interrupt controller of A/D Converter (ADC).
  • Page 31 Enable SFR: IP(Interrupt Priority Low) Read/Write Address: 0xB8H Default: 0000-0000 PPCA PLVDI PADC Name PPCA: = If set, Set priority for PCA interrupt higher PLVD: = If set, Set priority for Low Voltage interrupt higher PADC: = If set, Set priority for ADC interrupt highe PS: = If set, Set priority for serial port interrupt higher(UART) PT1: = If set, Set priority for timer1 interrupt higher PX1: = If set, Set priority for external interrupt 1 higher...
  • Page 32 IP and IPH are combined to form 4-level priority interrupt as the following table. Priority {IPH.x, IP.x} Level 1 (highest) http://www.DataSheet4U.net/ This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1 datasheet pdf - http://www.DataSheet4U.net/...
  • Page 33 Highest Priority Level Interrupt IP,IP2,IPH,IPH2 Registers IE, XICON,AUXIE Registers /INT0 /INT1 EXF2 IE2.1 SPIF IE.5 ADC_FLAG http://www.DataSheet4U.net/ IE2.0 CCF0 IE.6 ECCF0 CCF1 ECCF1 CCF2 Lowest Priority ECCF2 Level Interrupt Individual Enable S2RI S2TI Global Enable (IE.7) EPOF ELVD LVDF Interrupt Control Block STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...

  • Page 34: Watch Dog Timer

    Watch Dog Timer The watch dog timer in STC12C5Axx consists of an 8-bit pre-scalar timer and a 15-bit timer. The timer is one-time enabled by setting EN_WDT. Clearing ENW can not stop WDT counting. When the WDT is enabled, software should always reset the timer by writing 1 to CLR_WDT bit before the WDT overflows.
  • Page 35 IDL_WDT: = Behavior controller of the WDT while the device is put under idle 0: = (default) Stop Watch Dog Timer counting 1: = Keep Watch Dog Timer counting (so further reset could happen) {PS2, PS1, PS0}: selector of the WDT pre-scalar output. {0, 0, 0}: = set the pre-scaling value 2 {0, 0, 1}: = set the pre-scaling value 4 {0, 1, 0}: = set the pre-scaling value 8...

  • Page 36: Universal Asynchronous Serial Port (Uart)

    Universal Asynchronous Serial Port (UART) The serial port of STC12Cxx is duplex. It can transmit and receive simultaneously. The receiving and transmitting of the serial port share the same SFR SBUF, but actually there are two SBUF registers implemented in the chip, one is for transmitting and the other is for receiving.
  • Page 37 Mode3 Mode 3 is the same as mode 2 except the baud rate is variable. SMOD Baud Rate (for Mode 3) (Timer-1 overflow rate) In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register.
  • Page 38 bit. RI: = Receive done flag. After reception has been finished, the hardware will set this bit. http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...
  • Page 39 SFR: SBUF (Serial Buffer) Read/Write Address: 0x99H Default: 0000-0000 Name Frame Error Detection When used for frame error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0).

  • Page 40: Secondary Universal Asynchronous Serial Port (S2)

    The operation in Mode 2 for S2 is the same as the major UART in Mode 2. X BRT Baud Rate (for Mode 2) S2SMOD This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1 datasheet pdf - http://www.DataSheet4U.net/...
  • Page 41 Mode3 Mode 3 is the same as mode 2 except the baud rate is variable. Baud Rate (for Mode 3) (BRT timer overflow rate) S2SMOD The user can redirect functional pins RXD2 and RXD2 from pins P1.2 and P1.3 to pins P4.2 and P4.3 by setting bit S2P4 in SFR AUXR1.
  • Page 42 S2RB8 := In mode 2 and 3, the received 9th data bit will be put into this bit. S2TI := Transmitting done flag. After a transmitting has been finished, the hardware will set this bit. S2RI := Receive done flag. After reception has been finished, the hardware will set this bit. SFR: S2BUF Read/Write Address: 0x9BH...
  • Page 43 Set this bit to set the clock source for the secondary UART is BRT, or clear it to set the clock source for or the secondary UART as BRT/12. EXTRAM := 0: = On-chip auxiliary RAM is enabled and located at the address 0x0000 to 0x03FF. For address above 0x03FF, external RAM becomes the target automatically.
  • Page 44 T1CLKO := Setting this bit can enable timer 0 clock output on P3.5. The frequency of the output clock will be set as ( Timer 1 overflow rate / 2 ) TCLKO := Setting this bit can enable timer 0 clock output on P3.4. The frequency of the output clock will be set as ( Timer 0 overflow rate / 2 ) http://www.DataSheet4U.net/ STC12C5Axx Technical Summary...

  • Page 45: Programmable Counter Array (Pca)

    Programmable Counter Array (PCA) The Programmable Counter Array is a special 16-bit Timer that has two 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture (calculator of duty length for high/low pulse) software timer high-speed output pulse width modulator...
  • Page 46 Fosc/12 To PCA module Fosc/2 Timer0 overflow interrupt 16-bit counter External input ECI (P3.4) IDLE CMOD CIDL CPS1 CPS0 CCON CCF1 CCF0 PCA Timer/Counter SFR: CMOD (PCA Mode Control Register) Read/Write Address: 0xD9FH Default: 0XXX-X000 http://www.DataSheet4U.net/ CIDL CPS1 CPS0 Name CIDL := Behavior control of the PCA.
  • Page 47 If both bits are set, both edges will be enabled and a capture will occur for either transition. The bit ECOMn when set enables the comparator function. This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice.
  • Page 48 SFR: CL (PCA Base Counter Low Byte) Read/Write Address: 0XE9H Default: 0000-0000 Name SFR: CH (PCA Base Counter High Byte) Read/Write Address: 0XF9H Default: 00000-0000 Name SFR: CCAP0L (Low byte of PCA module-0 Compare/Capture register) Read/Write Address: 0XEAH Default: 0000-0000 Name SFR: CCAP0H (High byte of PCA module-0 Compare/Capture register) Read/Write...
  • Page 49 PWMn: = Enable plus width modulation mode n . 0 := (default) This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1...
  • Page 50 Inhibit the PWM functionality from module-n output to pin PWMn 1 := Enable the pin PWMn as the output of the PWM functionality from module-n http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...
  • Page 51 ECCFn: = Enable the CCFn flag in the CCON SFR to generate an interrupt. 0 := (default) Inhibit the interrupt(CCFn) from module-n to the MCU 1 := Permit the interrupt(CCFn) from module-n to the MCU Configure PCA Module ECOMn CAPPn CAPNn MATn TOGn PWMn...
  • Page 52 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOMn and MATn bits in the CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will be generated if the CCFn and ECCFn bits for the module are both set.
  • Page 53 Write to CCAPnL Write to CCAPnH CCON CCF1 CCF0 interrupt CCAPnH CCAPnL To CCFn 16-bit Enable MATCH comparator CCAPMn ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn PCA Software Timer Mode Write to CCAPnL Write to CCAPnH CCON CCF1 CCF0 http://www.DataSheet4U.net/ interrupt CCAPnH CCAPnL...
  • Page 54 C C A P n H E P C nH {0, C L [7:0]} < {E P CnL , C C A Pn L[7 :0]} C E X n C C A P nL E P C nL {0, C L [7:0 ]} >= {EP Cn L, C C A P nL[7:0 ]} E n able 9-B IT C O M P A R A T O R...

  • Page 55: Serial Peripheral Interface(Spi)

    This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice.
  • Page 56 other is keeping the clock signal low or high while the device idle which named phase. Permuting those states from polarity and phase, there could be four modes formed, they are SPI-MODE-0, SPI-MODE-1, SPI-MODE-2, SPI-MODE-3. Many device declares that they meet SPI mechanism, but few of them are adaptive to all four modes.
  • Page 57 1 := Set the SPCLK as HIGH while the communication is kept idle. That implies the leading edge of the clock is the falling edge, and the trailing edge is the falling rising edge. CPHA := Clock Phase 0 := (default) Data is driven when pin SS is low and changes on the trailing edge of SPCLK, and is sampled on the leading edge.
  • Page 58 The WCOL bit is set if the SPI data register SPIDAT is written during a data transfer. The WCOL flag is cleared in software by “writing 1 to this bit”. Configure the device to Master/Slave mode SPEN SSIG SS MSTR Mode MISO MOSI SPICLK Remark...
  • Page 59 Typical Connection MISO MISO MOSI MOSI Master Slave SPCLK SPCLK Port Pin SPI single master single slave configurartion MISO MISO MOSI MOSI Master/Slave Slave/Master SPCLK SPCLK SPI dual device configuarion, where either can be a master or a slave http://www.DataSheet4U.net/ MISO MISO MOSI...
  • Page 60 Communication In SPI, transfers are always initiated by the master. If the SPI is enabled(SPEN=1) and selected as master, any instruction that use SPI data register SPIDAT as the destination will starts the SPI clock generator and a data transfer. The data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after it.
  • Page 61 Typical Timing Diagram Clock Cycle SPCLK/CPOL=0 Driven from Master SPCLK/CPOL=1 Driven from Master DORD= MOSI (input) DORD= Driven from Master MOSI turns to input DORD= MISO (output) DORD= MISO turns to output SS pin (if SSIG bit = 0 ) Driven from Master SPI slave transfer format with CPHA=0 Clock...
  • Page 62 Clock Cycle SPICLK is strongly output- driving. SPCLK/CPOL=0 SPCLK/CPOL=1 SPEN=1 and MSTR=1, MOSI turns to output SPEN=0 or MSTR=0, MOSI switched not to data of SPI communication, also SPICLK output MISO turns to input data released from SPI data control DORD=0 MOSI (Output) DORD=1...

  • Page 63: Analog To Digital Converter

    Analog to Digital Converter ADC_CONTR ADC_POWE SPEE ADC_ ADC_ CHS2 CHS1 CHS0 SPEED1 FLAG START ADC_RESL ADC_RES P1.7(AIN7) P1.6(AIN6) P1.5(AIN5) P1.4(AIN4) P1.3(AIN3) P1.2(AIN2) P1.1(AIN1) P1.0(AIN0) Successive Approximation Regiter Comparator 10-bit DAC The ADC on STC12C5Axx an 10-bit resolution, successive-approximation approach, medium-speed http://www.DataSheet4U.net/ A/D converter.
  • Page 64 Set P1.6 as the A/D channel input {1,1,1} := Set P1.7 as the A/D channel input This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1...
  • Page 65 SFR: ADC_RES (ADC Value register): Read/Write Address: 0XBDH Default: 0000-0000 Name The ADC_RES is the final result from the A/D conversion. SFR: ADC_RESL (Low Byte of ADC Value register): Read/Write Address: 0XBEH Default: XXXX-XX00 Name The ADC_RESL (Low Bytes of ADC Value register http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...

  • Page 66: Power Management

    Power Management IDLE Mode An instruction setting PCON.0 causes the device go into the idle mode, the internal clock is gated off to the CPU but not to the interrupt, timer, PCA, SPI, ADC, WDT and serial port functions. There are two ways to terminate the idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the idle mode.
  • Page 67 POWER-DOWN Mode An instruction setting PCON.1 causes the device go into the POWER-DOWN mode. In the POWER-DOWN mode, the on-chip oscillator is stopped. The contents of on-chip RAM and SFRs are maintained. The power-down mode can be woken-up by either pin RST event or interrupt from INT0 or INT1.
  • Page 68 IDL: = Idle flag Set this bit to drive the device enter IDLE mode. http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...

  • Page 69: In System Programming And In Application Programming

    In System Programming and In Application Programming In System Programming (ISP) To develop a good program for ISP function, the user has to understand the architecture of the embedded flash. The embedded flash consists of 16 pages. Each page contains 512 bytes. Dealing with flash, the user must erase it in page unit before writing (programming) data into Erasing flash means setting the content of that flash as FFh.
  • Page 70 Mode Selection To Operate Standby AP-memory read AP-memory/Data-flash program AP-memory/Data-flash page erase SFR: IAP_TRIG (ISP Sequential Command register to trigger ISP/IAP operation) Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 ISP-Command / Device ID SFR: IAP_CONTR (IAP Control register) Bit-7 Bit-6 Bit-5 Bit-4...
  • Page 71 ) IAP_DATA Read a byte from flash This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1 datasheet pdf - http://www.DataSheet4U.net/...

  • Page 72: In-Application Program (Iap)

    EXCHANGE INDIRECT RAM WITH ACC XCHD A, @Ri EXCHANGE LOW-ORDER DIGIT INDIRECT RAM WITH ACC This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this product without notice. 2007/12 version A1...
  • Page 73 ARITHEMATIC OPERATIONS MNEMONIC DESCRIPTION ADD A, Rn ADD REGISTER TO ACC ADD A, direct ADD DIRECT BYTE TO ACC ADD A, @Ri ADD INDIRECT RAM TO ACC ADD A, #data ADD IMMEDIATE DATA TO ACC ADDC A, Rn ADD REGISTER TO ACC WITH CARRY ADDC A, direct ADD DIRECT BYTE TO ACC WITH CARRY ADDC A, @Ri...
  • Page 74 ANL C, /bit AND COMPLEMENT OF DIRECT BIT TO CARRY ORL C, bit OR DIRECT BIT TO CARRY ORL C, /bit OR COMPLEMENT OF DIRECT BIT TO CARRY MOV C, bit MOVE DIRECT BIT TO CARRY MOV bit, C MOVE CARRY TO DIRECT BIT BOOLEAN VARIABLE BRANCH MNEMONIC DESCRIPTION...

  • Page 75: Absolute Maximum Rating (Stc12C5Axx)

    Absolute Maximum Rating (STC12C5Axx) Parameter Rating Operating Voltage 4.5V ~ 5.5V Operating temperature under bias C ~ 85 Storage temperature C ~ 125 Voltage on any pin -0.5 ~ 5.5V Operating Frequency DC ~ 25MHz Tested by sampling DC Characteristics (STC12C5Axx) = 5.0V VSS = 0V, TA = 25 ℃...

  • Page 76: Absolute Maximum Rating (Stc12Le5Axx)

    Absolute Maximum Rating (STC12LE5Axx) Parameter Rating Operating Voltage 2.4V ~ 3.6V Operating temperature under bias C ~ 85 Storage temperature C ~ 125 Voltage on any pin -0.5 ~ 3.6V Operating Frequency DC ~ 25MHz Tested by sampling DC Characteristics (STC12LE5Axx) = 3.3V VSS = 0V, TA = 25 ℃...

  • Page 77: Package Dimension

    Package Dimension http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...
  • Page 78 Version History Version Date Page Description Initial issue 2008/09 http://www.DataSheet4U.net/ STC12C5Axx Technical Summary datasheet pdf - http://www.DataSheet4U.net/...

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