Timer 3 (Divided Clock Output) - STC micro STC8A8K64D4 Series Reference Manual

STC8A8K64D4 Series Manual
TM3ISR:
CPL
RETI
MAIN:
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SETB
JMP
END

13.5.25 Timer 3 (Divided clock output)

C language code
//Operating frequency for test is 11.0592MHz
#include "reg51.h"
#include "intrins.h"
sfr T4T3M =
sfr T4L =
sfr T4H =
sfr T3L =
sfr T3H =
sfr T2L =
sfr T2H =
sfr P0M1 =
sfr P0M0 =
sfr P1M1 =
sfr P1M0 =
sfr P2M1 =
sfr P2M0 =
sfr P3M1 =
sfr P3M0 =
sfr P4M1 =
sfr P4M0 =
P1.0
SP, #5FH
P0M0, #00H
P0M1, #00H
P1M0, #00H
P1M1, #00H
P2M0, #00H
P2M1, #00H
P3M0, #00H
P3M1, #00H
P4M0, #00H
P4M1, #00H
P5M0, #00H
P5M1, #00H
T3L,#66H
T3H,#0FCH
T4T3M,#0CH
IE2,#ET3
EA
$
0xd1;
0xd3;
0xd2;
0xd5;
0xd4;
0xd7;
0xd6;
0x93;
0x94;
0x91;
0x92;
0x95;
0x96;
0xb1;
0xb2;
0xb3;
0xb4;
;Test port
;65536-11.0592M/12/1000
;Set external counting mode and start timer
;Enable timer interrupt
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