STC micro STC8A8K64D4 Series Reference Manual page 13

STC8A8K64D4 Series Manual
23.5.9 UR1R_DMA Status Register (DMA_UR1R_STA) ...................................................................646
23.5.10 UR1R_DMA transfer total byte register (DMA_UR1R_AMT) ..............................................647
23.5.11 UR1R_DMA transfer complete byte register (DMA_UR1R_DONE) ....................................647
23.5.12 UR1R_DMA Receive Address Registers (DMA_UR1T_RXAx) ...........................................647
23.6 Data exchange between UART2 and memory (UR2T_DMA，UR2R_DMA) ..................................648
23.6.1 UR2T_DMA Configuration Register (DMA_UR2T_CFG) ......................................................648
23.6.2 UR2T_DMA Control Register (DMA_UR2T_CR) ..................................................................648
23.6.3 UR2T_DMA Status Register (DMA_UR2T_STA) ...................................................................648
23.6.4 UR2T_DMA transfer total byte register (DMA_UR2T_AMT) ................................................648
23.6.5 UR2T_DMA transfer complete byte register (DMA_UR2T_DONE) .......................................649
23.6.6 UR2T_DMA Send Address Registers (DMA_UR2T_TXAx) ..................................................649
23.6.7 UR2R_DMA Configuration Register (DMA_UR2R_CFG) .....................................................649
23.6.8 UR2R_DMA Control Register (DMA_UR2R_CR) ..................................................................649
23.6.9 UR2R_DMA Status Register (DMA_UR2R_STA) ...................................................................649
23.6.10 UR2R_DMA transfer total byte register (DMA_UR2R_AMT) ..............................................650
23.6.11 UR2R_DMA transfer complete byte register (DMA_UR2R_DONE) ....................................650
23.6.12 UR2R_DMA Receive Address Registers (DMA_UR2T_RXAx) ...........................................650
23.7 Data exchange between UART3 and memory (UR3T_DMA，UR3R_DMA) ..................................651
23.7.1 UR3T_DMA Configuration Register (DMA_UR3T_CFG) ......................................................651
23.7.2 UR3T_DMA Control Register (DMA_UR3T_CR) ..................................................................651
23.7.3 UR3T_DMA Status Register (DMA_UR3T_STA) ...................................................................651
23.7.4 UR3T_DMA transfer total byte register (DMA_UR3T_AMT) ................................................651
23.7.5 UR3T_DMA transfer complete byte register (DMA_UR3T_DONE) .......................................652
23.7.6 UR3T_DMA Send Address Registers (DMA_UR3T_TXAx) ..................................................652
23.7.7 UR3R_DMA Configuration Register (DMA_UR3R_CFG) .....................................................652
23.7.8 UR3R_DMA Control Register (DMA_UR3R_CR) ..................................................................652
23.7.9 UR3R_DMA Status Register (DMA_UR3R_STA) ...................................................................652
23.7.10 UR3R_DMA transfer total byte register (DMA_UR3R_AMT) ..............................................653
23.7.11 UR3R_DMA transfer complete byte register (DMA_UR3R_DONE) ....................................653
23.7.12 UR3R_DMA Receive Address Registers (DMA_UR3T_RXAx) ...........................................653
23.8 Data exchange between UART4 and memory (UR4T_DMA，UR4R_DMA) ..................................654
23.8.1 UR4T_DMA Configuration Register (DMA_UR4T_CFG) ......................................................654
23.8.2 UR4T_DMA Control Register (DMA_UR4T_CR) ..................................................................654
23.8.3 UR4T_DMA Status Register (DMA_UR4T_STA) ...................................................................654
23.8.4 UR4T_DMA transfer total byte register (DMA_UR4T_AMT) ................................................654
23.8.5 UR4T_DMA transfer complete byte register (DMA_UR4T_DONE) .......................................655
23.8.6 UR4T_DMA Send Address Registers (DMA_UR4T_TXAx) ..................................................655
23.8.7 UR4R_DMA Configuration Register (DMA_UR4R_CFG) .....................................................655
23.8.8 UR4R_DMA Control Register (DMA_UR4R_CR) ..................................................................655
23.8.9 UR4R_DMA Status Register (DMA_UR4R_STA) ...................................................................655
23.8.10 UR4R_DMA transfer total byte register (DMA_UR4R_AMT) ..............................................656
23.8.11 UR4R_DMA transfer complete byte register (DMA_UR4R_DONE) ....................................656
23.8.12 UR4R_DMA Receive Address Registers (DMA_UR4T_RXAx) ...........................................656
23.9 Data exchange between LCM and memory (LCM_DMA) ................................................................657
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