Spi_Dma Control Register (Dma_Spi_Cr); Spi_Dma Status Register (Dma_Spi_Sta) - STC micro STC8A8K64D4 Series Reference Manual

STC8A8K64D4 Series Manual
0: Disable SPI_DMA to send data. In master mode, SPI only sends clock to SCLK port, but does not read data
from XRAM, nor send data to MOSI port; in slave mode, SPI does not read data from XRAM, nor send data
to MISO port.
1: Enable SPI_DMA to send data. In master mode, SPI sends clock to SCLK port, and reads data from XRAM
and sends data to MOSI port; in slave mode, SPI reads data from XRAM and sends data to MISO port.
ACT_RX: SPI_DMA receive data control bit
0: Disable SPI_DMA to receive data. In master mode, SPI only sends clock to SCLK port, but does not read data
from MISO port, nor write data to XRAM; in slave mode, SPI does not read data from MOSI port, nor write
data to XRAM.
1: Enable SPI_DMA to receive data. In master mode, SPI sends clock to SCLK port, and reads data from MISO
port and writes data to XRAM; in slave mode, SPI reads data from MOSI port and writes XRAM.
SPIIP[1:0]: SPI_DMA interrupt priority control bits
SPIIP[1:0] Interrupt priority
00 Lowest (0)
01 Lower (1)
10 Higher (2)
11 Highest (3)
SPIPTY[1:0]：SPI_DMA Data bus access priority control bits
SPIPTY [1:0] Bus access priority
00 Lowest (0)
01 Lower (1)
10 Higher (2)
11 Highest (3)

23.4.2 SPI_DMA Control Register (DMA_SPI_CR)

Symbol Address
DMA_SPI_CR FA21H
ENSPI: SPI_DMA function enable control bit
0: Disable SPI_DMA function
1: Enable SPI_DMA function
TRIG_M: SPI_DMA master mode trigger control bit
0: Write 0 is invalid
1: Write 1 to start SPI_DMA master mode operation.
TRIG_S: SPI_DMA slave mode trigger control bit
0: Write 0 is invalid
1: Write 1 to start SPI_DMA slave mode operation.
CLRFIFO: Clear SPI_DMA receive FIFO control bit
0: Write 0 is invalid
1: Before starting the SPI_DMA operation, clear the built-in FIFO of SPI_DMA firstly.

23.4.3 SPI_DMA Status Register (DMA_SPI_STA)

Symbol Address
DMA_SPI_STA FA22H
SPIIF: SPI_DMA interrupt request flag bit. After the SPI_DMA data exchange is completed, the hardware automatically
sets SPIIF to 1. If the SPI_DMA interrupt is enabled, the interrupt service routine is entered. The flag bit needs to
be cleared by software.
RXLOSS: SPI_DMA receive data discard flag. During the SPI_DMA operation, when the XRAM bus is too busy to
clear the receive FIFO of the SPI_DMA and the data received by the SPI_DMA is automatically discarded, the
hardware automatically sets RXLOSS to 1. The flag bit needs to be cleared by software.
TXOVW: SPI_DMA data coverage flag. During the data transfer process of SPI_DMA, when the host mode SPI writes
the SPDAT register to trigger the SPI data transfer again, the data transfer will fail, and the hardware will
automatically set TXOVW to 1. The flag bit needs to be cleared by software.
B7 B6 B5
ENSPI TRIG_M TRIG_S
B7 B6 B5
- - -
B4 B3 B2
- - -
B4 B3 B2
- - TXOVW
B1 B0
- CLRFIFO
B1 B0
RXLOSS SPIIF
- 643 -