Adc Automatic Data Storage (Adc_Dma); Adc_Dma Configuration Register (Dma_Adc_Cfg); Adc_Dma Control Register (Dma_Adc_Cr); Adc_Dma Status Register (Dma_Adc_Sta) - STC micro STC8A8K64D4 Series Reference Manual

STC8A8K64D4 Series Manual

23.3 ADC Automatic Data Storage (ADC_DMA)

23.3.1 ADC_DMA Configuration Register (DMA_ADC_CFG)

Symbol Address
DMA_ADC_CFG FA10H
ADCIE: ADC_DMA interrupt enable control bit
0: Disable ADC_DMA interrupt
1: Enable ADC_DMA interrupt
ADCIP[1:0]: ADC_DMA interrupt priority control bits
ADCIP[1:0] Interrupt priority
00 Lowest (0)
01 Lower (1)
10 Higher (2)
11 Highest (3)
ADCPTY[1:0]：ADC_DMA Data bus access priority control bits
ADCPTY [1:0] Bus access priority
00 Lowest (0)
01 Lower (1)
10 Higher (2)
11 Highest (3)

23.3.2 ADC_DMA Control Register (DMA_ADC_CR)

Symbol Address
DMA_ADC_CR FA11H
ENADC: ADC_DMA function enable control bit
0: Disable ADC_DMA function
1: Enable ADC_DMA function
TRIG: ADC_DMA operation trigger control bit
0: Write 0 is invalid
1: Write 1 to start ADC_DMA operation.

23.3.3 ADC_DMA Status Register (DMA_ADC_STA)

Symbol Address
DMA_ADC_STA FA12H
ADCIF: ADC_DMA interrupt request flag bit. After ADC_DMA completes scanning all enabled ADC channels, the
hardware automatically sets ADCIF to 1. If the ADC_DMA interrupt is enabled, the interrupt service routine is
entered. The flag bit needs to be cleared by software.

23.3.4 ADC_DMA Receive Address Registers (DMA_ADC_RXAx)

Symbol Address
DMA_ADC_RXAH FA17H
DMA_ADC_RXAL FA18H
DMA_ADC_RXA: Set the storage address of ADC conversion data during ADC_DMA operation.

23.3.5 ADC_DMA Configuration Register 2 (DMA_ADC_CFG2)

Symbol Address
DMA_ADC_CFG2 FA19H
CVTIMESEL[3:0]: Set the number of ADC conversions for each ADC channel during ADC_DMA operation.
B7 B6 B5
ADCIE -
B7 B6 B5
ENADC TRIG -
B7 B6 B5
- - -
B7 B6 B5
B7 B6 B5
- - -
B4 B3 B2
ADCIP[1:0]
B4 B3 B2
- - -
B4 B3 B2
- - -
B4 B3 B2
ADDR[15:8]
ADDR[7:0]
B4 B3 B2
- CVTIMESEL[3:0]
B1 B0
ADCPTY[1:0]
B1 B0
- -
B1 B0
- ADCIF
B1 B0
B1 B0
- 639 -