STC micro STC8A8K64D4 Series Reference Manual page 178

STC8A8K64D4 Series Manual
CCAPM3 PCA3 Mode Control Register
CCAP3L PCA3 low byte
CCAP3H PCA3 high byte
PCA_PWM3 PCA3 的 PWM mode register
I/O port interrupt priority low
PINIPL
register
I/O port interrupt priority high
PINIPH
register
CHIPID0 Hard ID0
CHIPID1 Hard ID1
CHIPID2 Hard ID2
CHIPID3 Hard ID3
CHIPID4 Hard ID4
CHIPID5 Hard ID5
CHIPID6 Hard ID6
CHIPID7 Hard ID7
CHIPID8 Hard ID8
CHIPID9 Hard ID9
CHIPID10 Hard ID10
CHIPID11 Hard ID11
CHIPID12 Hard ID12
CHIPID13 Hard ID13
CHIPID14 Hard ID14
CHIPID15 Hard ID15
CHIPID16 Hard ID16
CHIPID17 Hard ID17
CHIPID18 Hard ID18
CHIPID19 Hard ID19
CHIPID20 Hard ID20
CHIPID21 Hard ID21
CHIPID22 Hard ID22
CHIPID23 Hard ID23
CHIPID24 Hard ID24
CHIPID25 Hard ID25
CHIPID26 Hard ID26
CHIPID27 Hard ID27
CHIPID28 Hard ID28
CHIPID29 Hard ID29
CHIPID30 Hard ID30
CHIPID31 Hard ID31
M2M_DMA control register
DMA_M2M_CR
M2M_DMA status register
DMA_M2M_STA
M2M_DMA total
DMA_M2M_AMT
transferred
M2M_DMA transfer completed bytes
DMA_M2M_DONE
M2M_DMA send address high byte
DMA_M2M_TXAH
M2M_DMA send address low byte
DMA_M2M_TXAL
M2M_DMA receive address high
DMA_M2M_RXAH
byte
M2M_DMA receive address low byte
DMA_M2M_RXAL
ADC_DMA configuration register
DMA_ADC_CFG
ADC_DMA control register
DMA_ADC_CR
ADC_DMA status register
DMA_ADC_STA
ADC_DMA receive address high
DMA_ADC_RXAH
byte
ADC_DMA receive address low byte
DMA_ADC_RXAL
ADC_DMA configuration register 2
DMA_ADC_CFG2
ADC_DMA channel enable 0
DMA_ADC_CHSW0
ADC_DMA channel enable 1
DMA_ADC_CHSW1
SPI_DMA configuration register
DMA_SPI_CFG
SPI_DMA control register
DMA_SPI_CR
SPI_DMA status register
DMA_SPI_STA
SPI_DMA total bytes
DMA_SPI_AMT
transferred
SPI_DMA transfer completed bytes
DMA_SPI_DONE
SPI_DMA send address high byte
DMA_SPI_TXAH
SPI_DMA send address low byte
DMA_SPI_TXAL
SPI_DMA receive address high byte
DMA_SPI_RXAH
SPI_DMA receive address low byte
DMA_SPI_RXAL
SPI_DMA configuration register 2
DMA_SPI_CFG2
UR1T_DMA configuration register
DMA_UR1T_CFG
UR1T_DMA control register
DMA_UR1T_CR
UR1T_DMA status register
DMA_UR1T_STA
UR1T_DMA total
DMA_UR1T_AMT
transferred
UR1T_DMA transfer
DMA_UR1T_DONE
bytes
UR1T_DMA send address high byte
DMA_UR1T_TXAH
UR1T_DMA send address low byte
DMA_UR1T_TXAL
UR1R_DMA configuration register
DMA_UR1R_CFG
UR1R_DMA control register
DMA_UR1R_CR
FD54H -
FD55H
FD56H
FD57H EBS3[1:0]
FD60H P7IP
FD61H P7IPH
FDE0H
FDE1H
FDE2H
FDE3H
FDE4H
FDE5H
FDE6H
FDE7H
FDE8H
FDE9H
FDEAH
FDEBH
FDECH
FDEDH
FDEEH
FDEFH
FDF0H
FDF1H
FDF2H
FDF3H
FDF4H
FDF5H
FDF6H
FDF7H
FDF8H
FDF9H
FDFAH
FDFBH
FDFCH
FDFDH
FDFEH
FDFFH
FA01H ENM2M
FA02H -
bytes to be
FA03H
FA04H
FA05H
FA06H
FA07H
FA08H
FA10H ADCIE
FA11H ENADC
FA12H -
FA17H
FA18H
FA19H -
FA1AH CH15
FA1BH CH7
FA20H SPIIE
FA21H ENSPI
FA22H -
to be
FA23H
FA24H
FA25H
FA26H
FA27H
FA28H
FA29H -
FA30H UR1TIE
FA31H ENUR1T
FA32H -
bytes to be
FA33H
completed
FA34H
FA35H
FA36H
FA38H UR1RIE
FA39H ENUR1R
ECOM3 CCAPP3 CCAPN3
XCCAP3H[1:0]
P6IP P5IP P4IP
P6IPH P5IPH P4IPH
- -
TRIG
- - -
- - -
- -
TRIG
- - -
- - -
CH14 CH13 CH12
CH6 CH5 CH4
ACT_TX ACT_RX -
TRIG_S -
TRIG_M
- - -
- - -
- - -
-
-
TRIG
- - -
- - -
- TRIG -
-
MAT3 TOG3 PWM3
XCCAP3L[1:0] EPC3H
P3IP P2IP P1IP
P3IPH P2IPH P1IPH
- - -
- - -
ADCMIP[1:0] ADCPTY[1:0]
- - -
- - -
CVTIMESEL[3:0]
CH11 CH10 CH9
CH3 CH2 CH1
SPIIP[1:0] SPIPTY[1:0]
- - -
- TXOVW RXLOSS
- WRPSS
UR1TIP[1:0] UR1TPTY[1:0]
- -
-
- TXOVW -
UR1RIP[1:0] UR1RPTY[1:0]
- - -
ECCF3 x000,0000
0000,0000
0000,0000
EPC3L 0000,0000
P0IP 0000,0000
P0IPH 0000,0000
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
nnnn,nnnn
-
00xx,xxxx
M2MIF xxxx,xxx0
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0xxx,0000
-
00xx,xxxx
ADCIF xxxx,xxx0
0000,0000
0000,0000
xxxx,0000
CH8 1000,0000
CH0 0000,0001
000x,0000
CLRFIFO
000x,xxx0
SPIIF xxxx,x000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
SSS[1:0] xxxx,x000
0xxx,0000
-
00xx,xxxx
UR1TIF xxxx,x0x0
0000,0000
0000,0000
0000,0000
0000,0000
0xxx,0000
CLRFIFO 0x0x,xxx0
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