Usb - ADLINK Technology arm AMPERE COM-HPC-ALT User Manual

COM-HPC-ALT User's Guide
PCIe_REFCLK1- E93
PCIe_REFCLK1+ E94
PCIe_REFCLK2- F92
PCIe_REFCLK2+ F93
PCIe_REFCLK3- G93
PCIe_REFCLK3+ G94
PCIe_CLKREQ0_LO# A56
PCIe_CLKREQ0_HI# A57
PCIe_CLKREQ0_1# E96
PCIe_CLKREQ0_2# E97
PCIe_CLKREQ0_3# F95

4.3.4 USB

The COM-HPC Server Module supports up to eight USB 2.0 ports, up to two USB 3.2 Gen1 or Gen2 ports and up to two USB 3.2 Gen2x2 ports or USB4
ports. A USB 3.2 Gen2x2 may be used as USB 3.2 Gen1 or Gen2 port as well.
To realize a COM-HPC USB 3.2 Gen1, Gen2, Gen2x2 or USB4 port, one of the four available USB 2.0 ports from the USB[0:3] pool must be used along
with the SuperSpeed pins. The specific pairings noted in table below need to be made.
Name Pin #
USB0+ D17
USB0- D16
USB1+ D14
USB1- D13
USB2+ C18
Page 18
Reference clock pair for PCIe lanes [16:31], also
referred to PCIe Group 1
Reference clock pair for PCIe lanes [32:47], also
referred to PCIe Group 2
Reference clock pair for PCIe lanes [48:63], also
referred to PCIe Group 2
PCIe reference clock request signals from Carrier
devices for PCIe_REFCLK0_LO clock pair
PCIe reference clock request signals from Carrier
devices for PCIe_REFCLK0_HI clock pair
PCIe reference clock request signals from Carrier
devices for PCIe_REFCLK1 clock pair
PCIe reference clock request signals from Carrier
devices for PCIe_REFCLK2 clock pair
PCIe reference clock request signals from Carrier
devices for PCIe_REFCLK3 clock pair
Description
USB 2.0 differential pairs, channels 0 through 7.
USB0 may be configured as a USB client or as a host,
or both at the Module designer's discretion. All other
USB ports, if implemented, shall be host ports.
Copyright © 2023 ADLINK Technology, Inc.
O PCIe
O PCIe
O PCIe
I/O OD PU 10K
3.3V
I/O OD PU 10K
3.3V
I/O OD PU 10K
3.3V
I/O OD PU 10K
3.3V
I/O OD PU 10K
3.3V
I/O PU / PD Comment
I/O USB 1.1/2.0 compliant
3.3VSB
This product only support USB0-3 through a PCIe to USB IC
PICMG COM-HPC R1.0