Signal Descriptions On J1/J2 Connectors; Ethernet Kr/Kx - ADLINK Technology arm AMPERE COM-HPC-ALT User Manual

COM-HPC-ALT User's Guide

4.3 Signal Descriptions on J1/J2 Connectors

4.3.1 Ethernet KR/KX

Ethernet KR interface are defined for COM-HPC. For these ports, the Ethernet MACs are located on COM-HPC module. PHYs (if used) are on the Carrier.
In some cases, no PHY is required, for short cable ("Direct Attach" cables) or Carrier runs.
COM-HPC support both of MDIO and I2C control interfaces for the PHYs. The MDIO and I2C control interfaces are grouped into quads, for KR ports 0:3
and ports 4:7
Name Pin #
ETH0_TX- C20
ETH0_TX+ C21
ETH1_TX- C23
ETH1_TX+ C24
ETH2_TX- C26
ETH2_TX+ C27
ETH3_TX- C29
ETH3_TX+ C30
ETH0_RX- D19
ETH0_RX+ D20
ETH1_RX- D22
ETH1_RX+ D23
ETH2_RX- D25
ETH2_RX+ D26
ETH3_RX- D28
ETH3_RX+ D29
ETH0-3_MDIO_DAT H99
ETH0-3_MDIO_CLK H98
ETH0-3_INT# G99
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Description
Ethernet KR ports, transmit output differential pairs.
Ethernet KR ports, receive input differential pairs.
Management Data I/O interface mode data signal for
serial data transfers between the MAC and an
external PHY for ETHx ports 0 to 3
Clock signal for Management Data I/O interface
mode data signal for serial data transfers between the
MAC and an external PHY for ETHx ports 0 to 3
Active low interrupt signal from IO Port expanders for
ETH ports 0 to 3
Copyright © 2023 ADLINK Technology, Inc.
I/O PU / PD Comment
O AC coupled Off Module
KR
I AC coupled Off Module
KR
I/O PU 2K2
3.3VSB
O
3.3VSB
I PU 2K2
3.3VSB
PICMG COM-HPC R1.0