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COM-HPC-ALT User's Guide
PCIe50_RX+
F75
PCIe50_RX-
F74
PCIe51_RX+
F78
PCIe51_RX-
F77
PCIe52_RX+
F81
PCIe52_RX-
F80
PCIe53_RX+
F84
PCIe53_RX-
F83
PCIe54_RX+
F87
PCIe54_RX-
F86
PCIe55_RX+
F90
PCIe55_RX-
F89
PCIe56_RX+
G70
PCIe56_RX-
G69
PCIe57_RX+
G73
PCIe57_RX-
G72
PCIe58_RX+
G76
PCIe58_RX-
G75
PCIe59_RX+
G79
PCIe59_RX-
G78
PCIe60_RX+
G82
PCIe60_RX-
G81
PCIe61_RX+
G85
PCIe61_RX-
G84
PCIe62_RX+
G88
PCIe62_RX-
G87
PCIe63_RX+
G91
PCIe63_RX-
G90
PCIe_BMC_TX-
A59
PCIe_BMC_TX+
A60
PCIe_BMC_RX-
B58
PCIe_BMC_RX+
B59
PCIe_REFCLK0_LO-
C59
PCIe_REFCLK0_LO+
C60
PCIe_REFCLK0_HI-
C57
PCIe_REFCLK0_HI+
C56
Page 17
PCI Express Differential Transmit Pair for Carrier BMC
(Board Management Controller)
PCI Express Differential Transmit Pair for Carrier BMC
(Board Management Controller)
Reference clock pair for PCIe lanes [0:7], also referred
to PCIe Group 0 Low and for the PCIe_BMC link
Reference clock pair for PCIe lanes [8:15], also
referred to PCIe Group 0 High
Copyright © 2023 ADLINK Technology, Inc.
O PCIe
AC coupled on Module
I PCIe
AC coupled off Module
O PCIe
O PCIe
PICMG COM-HPC R1.0
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