ADLINK Technology arm AMPERE COM-HPC-ALT User Manual page 58

COM-HPC-ALT User's Guide
2 The Module only drives WD_OUT pin high until cleared by Module software.
3 The Module generates an NMI. The WD_OUT pin is driven high until cleared by Module
software.
The watchdog output shall come up as a logic low and shall be disabled upon power-on-reset (VCC power cycle) or external system reset (when
RSTBTN# pin is toggled low by external hardware). The watchdog may be enabled by BIOS or system software.
WD_STROBE#
Typically, the watchdog parameters (output options, enabling, enable delay, timeout delay) are managed by the Module BIOS, often via a BIOS setup
screen. The regular watchdog software strobes to prevent a watchdog timeout are typically handled by the Module's application software. There may
be API abstractions to isolate the application software from the watchdog hardware.
In COM-HPC (unlike COM-Express), there is a hardware strobe option. Carrier board hardware may periodically drive ("strobe") the Module
WD_STROBE# input pin low to keep the watchdog from timing out.
The software and hardware strobes should be implemented as a logical OR by the Module design, so that either method may be used, or both, to keep
the watchdog from timing out.
The software programmable Watchdog Enable Delay is the time between when the watchdog is enabled by firmware and when the first watchdog
strobe is needed to prevent a watchdog time out. The enable delay allows time for the operating system to boot and the application to load and
initialize. This feature is sometimes referred to as a "two stage" watchdog. After the initial Enable Delay, the enabled watchdog must be periodically
strobed by software to prevent a watchdog timeout. The Strobe Interval shall be software programmable. Recommended ranges in enable delay and
max strobe periods are given in the following table.
Min Value
Enable Delay 1 second
Strobe Interval 0.1 second
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Max Value
10 minutes
10 minutes
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PICMG COM-HPC R1.0