ADLINK Technology arm AMPERE COM-HPC-ALT User Manual page 15

COM-HPC-ALT User's Guide PICMG COM-HPC R1.0
I2C
2x I2C, I2C 0 and I2C 1
I2C 0 additional offer ALERT# input and 3.3V power rail (source from Ampere Altra SoC)
I2C 1 is 1.8V power rail (source from Ampere Altra SoC)
Supports software programmable clock of 100 KHz (standard mode) and 400 KHz operation (fast mode)
Supports multi-master, allowing carrier to read the module's EEPROM before powering up the module
Support 7-bit and 10-bit address mode
An EEPROM is located on I2C 0, which can be used as Module EEPROM and IPMI FRU, combined together
USB_PD_I2C
COM-HPC Module should support exporting Port 80 information over the USB_PD I2C bus (signals USB_OD_I2C_DAT and USB_PD_I2C_CLK) to Carrier
hardware that implements a pair of 7-segment displays to show the codes
The USB_PD_I2C comes from MMC ATMEGA128 and USB_PD_I2C, MMC and SOC connect to the same bus
IPMB
1x IPMB comes from MMC. Please refer to section 2.9 Module Management Controller for further details
IPMB is used with a Carrier BMC.
MMC is ATMEGA solution that communicate with Ampere Altra SOC through UART
Several monitored voltage (for example, memory voltage, CPU voltage) and temperature (for example, CPU temperature) can be communicated
between MMC and Carrier BMC through IPMB.
A dedicated PCIe x1 lane is also available on the Carrier BMC, allowing the Carrier BMC to generate a VGA or other format video output, for
management functions.
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