Part 7.2: Expansion Port J10 - Alinx AC7010C User Manual

Figure 7-2: PL User LEDs on the FPGA Core Board
PL User LEDs pin assignment:
Signal Name ZYNQ Pin Name
LED2

Part 7.2: Expansion Port J10

The expansion port J10 is a 40-pin 2.54mm double-row connector, which
expands more peripherals and interfaces for users.
the user can solder to a double-row male connectors or female connectors as
needed.
The expansion port has 40 signals, of which 1-channel 5V power supply,
2-channel 3.3 V power supply, 3-channle ground and 34 IOs. Among the 34 IO
signals, 26 of them are connected to the IO of the BANK34 of the ZYNQ PL.
The PCB design is differentially connected. The default level is 3.3V. The user
can change the IO level of the BANK34 by replacing the power chip (U20) on
the core board. In addition, there are 8 IO ports connected to the MIO of the PS
terminal, and the level standard is 3.3V.
Do not directly connect the IO directly to the 5V device to avoid
burning the FPGA. If you want to connect 5V equipment, you need to
connect level conversion chip.
The circuit of the expansion port (J10) is shown in Figure 7-3:
www.alinx.com
ZYNQ Pin Number
IO_0_34
AC7010C / AC7020C User Manual
R19 PL User LED PL LED2
The default is not soldered,
Description
32 / 40