Alinx AC7010C User Manual page 26

Figure 6-6: The connection between Zynq7000 and USB chip
Figure 6-7 shows the physical diagram of the USB2.0 part. U11 is
USB3320C, J3 is the Host USB interface, and J4 is the OTG USB interface.
Jumper caps J5 and J6 are used for Host and OTG mode selection.
Figure 6-7: The USB3320C chip on the FPGA Board
USB2.0 Pin Assignment：
Signal Name
OTG_DATA4
OTG_DIR
OTG_STP
OTG_NXT
OTG_DATA0
OTG_DATA1
OTG_DATA2
OTG_DATA3
OTG_CLK
OTG_DATA5
OTG_DATA6
OTG_DATA7
OTG_RESETN
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ZYNQ Pin Name ZYNQ Pin Number
PS_MIO28_501
PS_MIO29_501
PS_MIO30_501
PS_MIO31_501
PS_MIO32_501
PS_MIO33_501
PS_MIO34_501
PS_MIO35_501
PS_MIO36_501
PS_MIO37_501
PS_MIO38_501
PS_MIO39_501
PS_MIO46_501
AC7010C / AC7020C User Manual
C16
C13 USB Data Direction Signal
C15
E16 USB Next Data Signal
A14
D15
A12
F12
A11
A10
E13
C18
D16
Description
USB Data Bit4
USB Stop Signal
USB Data Bit0
USB Data Bit1
USB Data Bit2
USB Data Bit3
USB Clock Signal
USB Data Bit5
USB Data Bit6
USB Data Bit7
USB Reset Signal
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