Part 5.2: Pl System Clock Source; Part 6：Zynq Processor System (Ps) Peripherals - Alinx AC7010C User Manual

Figure 5-1: Active crystal oscillator to the PS section
PS Clock Pin Assignment

Part 5.2: PL system clock source

The AC7010C/AC7020C FPGA core board, The PL system clock on the
AC7010C/AC7020C core board is powered by a 50MHz active crystal. This
50Mhz clock can be used to drive user logic in the FPGA. The schematic
diagram of the clock source is shown in Figure 5-3.
PL Clock pin assignment:
Part 6：ZYNQ Processor System (PS) peripherals
ZYNQ is composed of the PS part of the ARM system and the PL part of
the FPGA logic. Some peripherals on the FPGA core board are connected to
the IO of the PS, and some peripherals are connected to the IO of the PL. First
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Signal Name
PS_CLK_500
Figure 5-3: PL system clock source
Signal Name
500_CLK
AC7010C / AC7020C User Manual
ZYNQ Pin
E7
ZYNQ Pin
U18
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