Part 4: Zynq Chip - Alinx AC7010C User Manual

VCCI35 power supplies are generated by the three LDOs "SPX3819M5-3-3",
the VCCIO34 is powered by the BANK34 of ZYNQ, and the VCCIO35 is
powered by the BANK35 of ZYNQ. By replacing with other LDO chips, BANK34
and BANK35IO adapts to different voltage standards. +1.5V Generates VTT
and VREF voltages required by DDR3 via TI's TPS51200
The functions of each power distribution are shown in the following table
below:
Power Supply
+1.0V
+1.5V
+1.8V
+3.3V
VREF, VTT
VCCIO34
VCCIO35
Because the power supply of the PS and PL parts of ZYNQ has the
power-on sequence requirements, in the circuit design, we have designed
according to the power requirements of ZYQN. The power-on sequence is
+1.0V->+1.8V->+1.5 V-> (3.3V, VCCIO34, VCCIO35). Figure 3-2 shows the
circuit design of the power supply:
In the PCB design, an 8-layer PCB is used, and a separate power supply
layer and GND layer are reserved, so that the power supply of the entire
development board has very good stability.

Part 4: ZYNQ Chip

The Core development board uses Xilinx's Zynq7000 series chip,
AC7010C chip model is XC7Z010-1CLG400C (AC7020C chip model is
XC7Z020-2CLG400I). The chip's PS system integrates two ARM CortexTM-A9
processors, AMBA® interconnects, internal memory, external memory
www.alinx.com
AC7010C / AC7020C User Manual
ZYNQ Core Voltage
DDR3, ZYNQ Bank502
ZYNQ auxiliary voltage, ZYNQ PLL, ZYNQ BANK501, VCCIO,
Ethernet, USB 2.0
ZYNQ VCCIO, Gigabit Ethernet, Serial Port, HDMI, RTC,
FLASH,EEPROM SD Card
Function
DDR3
ZYNQ Bank34
ZYNQ Bank35
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