Part 4.1: Jtag Interface - Alinx AC7010C User Manual

Figure 4-2: The XC7Z010 chip on the Core Board AC7010C

Part 4.1: JTAG Interface

First, let's talk about the JTAG debug interface (J14) of the
AC7010C/AC7020C core board. Users can debug and download the ZYNQ
program by connecting the ALINX Xilinx USB Cable downloader. Figure 4-3
shows the schematic part of the JTAG port, which involves four signals, TCK,
TMS, TDO, and TDI. These four signals are connected to the JTAG pins of
BANK0 of the Zynq7010 (Zynq7020) chip (TCK_0, TMS_0, TDO_0 and TDI_0)
The JTAG interface uses a 14-pin 0.06 inch standard connector, and
Figure 4-4 detailed JTAG interface on the core board.
Figure 4-4: The JTAG on the FPGA Core Board
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Figure 4-3: The JTAG port schematic
AC7010C / AC7020C User Manual
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