Xilinx ML365 Virtex-II Pro QDR II SRAM M Manuals

Manuals and User Guides for Xilinx ML365 Virtex-II Pro QDR II SRAM M. We have 1 Xilinx ML365 Virtex-II Pro QDR II SRAM M manual available for free PDF download: User Manual

Xilinx ML365 Virtex-II Pro QDR II SRAM M User Manual (104 pages)

QDR II SRAM (200 MHz) Memory Board

Brand: Xilinx | Category: Storage | Size: 2 MB

Guide Contents

3
Additional Resources

3
Conventions

4
- Typographical
  4
- Online Document
  4
- Table of Contents
  5
Schedule of Figures

7
Chapter 2: Architecture

9
Schedule of Tables

9
- Chapter 1: Introduction
  11
Chapter 1: Introduction

9
Chapter 3: Electrical Requirements

9
Chapter 4: Signal Integrity Recommendations and Simulations

9
- Figure 1-1: Simplified Block Diagram of Memory Board Interface
  
  11
- Overview
  
  11
- Features
  
  12
- Figure 2-1: ML365 Board Block Diagram
  
  13
Chapter 2: Architecture

13
- ML365 Board Block Diagram
  
  13
- Block Descriptions
  
  14
  - Clocks
    14
    
    200 Mhz LVPECL Clock (Y1)
    14
    
    250 Mhz LVPECL Clock (Y2)
    14
    
    SMA Clock Connectors
    15
  - Fpga
    14
  - Memories
    14
    
    QDR II SRAM (U5, Banks 6 and 7)
    14
    
    QDR II SRAM (U11, Banks 2 and 3)
    14
    
    QDR II SRAM (U12, Banks 0 and 1)
    14
  - Rs232 (J5)
    14
  - User I/Os
    15
    
    Gpio (P19)
    15
    
    DIP Switch (SW3)
    16
    
    Leds
    16
    
    Push Buttons
    17
    
    Rotary Switch
    17
    
    Power on or off Slide Switch
    17
    
    Jumper Settings
    17
    
    Grounded I/Os
    17
  - Figure 2-2: LCD Write Timing Diagram
    
    18
  - Liquid Crystal Display
    18
    
    Write Cycle for the LCD
    18
  - Display Commands
    19
- Figure 2-3: Display Initialization Sequence
  
  21
- Figure 2-4: LCD Panel Character Set
  
  22
- Power
  
  23
  - Power Distribution
    23
  - Input Voltage
    23
  - 3.3 V Generation
    23
- FPGA Configuration
  
  24
  - Selecting the Configuration Mode
    24
  - Serial Configuration
    24
    
    Master Serial Mode
    24
    
    Slave Serial Mode
    24
  - Selectmap Configuration
    25
  - Systemace Configuration (Default Mode)
    25
  - Figure 2-5: Selectmap Connectors P99 and P111
    
    26
  - JTAG Configuration
    27
- Figure 2-6: Systemace and JTAG Connectors
  
  27
- Figure 2-7: JTAG I/O Connector P103
  
  28
Chapter 3: Electrical Requirements

29
Chapter 5 : Board Layout Guidelines

47
Appendix 1: Related Documentation

53
Appendix 2: FPGA Pinout

55
Appendix 3: Memory Board Schematics and Characterization Results

75
- Schematics
  
  75
- Characterization Results
  
  104
  - Long-Term Runs
    104
  - Corners Results Matrix
    104

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Xilinx ML365 Virtex-II Pro QDR II SRAM M Manuals

Xilinx ML365 Virtex-II Pro QDR II SRAM M User Manual (104 pages)

Table of Contents

Guide Contents

Additional Resources

Conventions

Schedule of Figures

Chapter 2: Architecture

Schedule of Tables

Chapter 1: Introduction

Chapter 3: Electrical Requirements

Chapter 4: Signal Integrity Recommendations and Simulations

Figure 1-1: Simplified Block Diagram of Memory Board Interface

Overview

Features

Figure 2-1: ML365 Board Block Diagram

Chapter 2: Architecture

ML365 Board Block Diagram

Block Descriptions

Figure 2-2: LCD Write Timing Diagram

Figure 2-3: Display Initialization Sequence

Figure 2-4: LCD Panel Character Set

Power

FPGA Configuration

Figure 2-5: Selectmap Connectors P99 and P111

Figure 2-6: Systemace and JTAG Connectors

Figure 2-7: JTAG I/O Connector P103

Chapter 3: Electrical Requirements

Power Consumption

FPGA Internal Power Budget

Termination and Transmission Line Summaries

Terminations and Transmission Lines for QDR Components

IBIS Simulations

Figure 4-1: Signal Terminations for Transmitted and Received Data

Figure 4-2: Data Signal Bit 4 from the FPGA to the Memory (Typical Case)

Figure 4-3: Eye Diagram for Data Bit 4 from the FPGA to the QDR II SRAM, U11

Figure 4-4: Data Signals from the QDR II SRAM U11 at the FPGA

Slow/Weak and Fast/Strong Cases)

Figure 4-5: Eye Diagram for Data Bit 4 at the FPGA from Component U11

Clock Signal Simulations

Figure 4-6: Clock Signal Terminations

Figure 4-7: Clock K Signal from the FPGA to the QDR II SRAM, Component U11

Figure 4-8: Clock CQ Signal from the FPGA to the QDR II SRAM Component U11

Figure 4-9: Address and Control Signal Terminations

Address and Control Signal Simulations

Figure 4-10: Address/Control Signals for the QDR II SRAM, Component U11, Bit 4

Chapter 5 : Board Layout Guidelines

Decoupling Guidelines

Providing Additional Ground Pins

Board Stackup Guidelines

Figure 5-1: Picture of the Top Layer of the ML365 Revision 1.0B Board

Figure 5-2: Picture of the Bottom Layer of the ML365 Revision 1.0B Board

Appendix 1: Related Documentation

Appendix 2: FPGA Pinout

Appendix 3: Memory Board Schematics and Characterization Results

Schematics

Characterization Results

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