Rtc Interrupt Flag Register - Epson S1C17W12 Technical Manual

9 REAL-TIME CLOCK (RTCA)
Table 9.6.2 Correspondence between the count value and day of the week
Note: Be sure to avoid writing to the RTCYAR.RTCWK[2:0] bits while the RTCCTL.RTCBSY bit = 1.
Bits 7–4 RTCYH[3:0]
Bits 3–0 RTCYL[3:0]
The RTCYAR.RTCYH[3:0] bits and the RTCYAR.RTCYL[3:0] bits are used to set and read the 10-
year digit and the 1-year digit of the year counter, respectively. The setting/read values are a BCD
code within the range from 0 to 99.
Note: Be sure to avoid writing to the RTCYAR.RTCYH[3:0]/RTCYL[3:0] bits while the RTCCTL.
RTCBSY bit = 1.

RTC Interrupt Flag Register

Register name Bit
RTCINTF 15
14
13
12
11–9 –
8
7
6
5
4
3
2
1
0
Bit 15 RTCTRMIF
Bit 14 SW1IF
Bit 13 SW10IF
Bit 12 SW100IF
These bits indicate the real-time clock interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
RTCINTF.RTCTRMIF bit: Theoretical regulation completion interrupt
RTCINTF.SW1IF bit:
RTCINTF.SW10IF bit:
RTCINTF.SW100IF bit:
Bits 11–9 Reserved
9-12
RTCYAR.RTCWK[2:0] bits
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
RTCTRMIF 0
SW1IF 0
SW10IF 0
SW100IF 0
0x0
ALARMIF 0
1DAYIF 0
1HURIF 0
1MINIF 0
1SECIF 0
1_2SECIF 0
1_4SECIF 0
1_8SECIF 0
1_32SECIF 0
Stopwatch 1 Hz interrupt
Stopwatch 10 Hz interrupt
Stopwatch 100 Hz interrupt
Seiko Epson Corporation
Day of the week
Saturday
Friday
Thursday
Wednesday
Tuesday
Monday
Sunday
Reset R/W
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
H0 R/W
– R –
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
S1C17W12/W13 TECHNICAL MANUAL
Remarks
(Rev. 1.2)