Epson S1C17W12 Technical Manual page 42

2 POWER SUPPLY, RESET, AND CLOCKS
Transition takes place automatically by the
initial boot sequence after a request from
the reset source is canceled.
OSC1
HALT
OSC1
RUN
Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram
Canceling HALT or SLEEP mode
The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and
put the CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request.
• Interrupt request from a peripheral circuit
• NMI from the watchdog timer
• Debug interrupt
• Reset request
2-16
RESET
(Initial state)
IOSC
RUN
CLGSCLK.CLKSRC[1:0] = 0x3
OSC3
RUN
OSC3
HALT
Seiko Epson Corporation
IOSC
HALT
SLEEP
CLGSCLK.CLKSRC[1:0] = 0x1
EXOSC
∗ In RUN and HALT modes, the clock sources not used
as SYSCLK can be all disabled.
S1C17W12/W13 TECHNICAL MANUAL
slp instruction
RUN SLEEP
HALT/SLEEP
cancelation signal
(wake-up)
Debug interrupt
RUN/
HALT/ DEBUG
retd instruction
RUN
EXOSC
HALT
(Rev. 1.2)