Operations; Initialization - Epson S1C17W12 Technical Manual

Cmos 16-bit single chip microcontroller
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12 UART (UART2)
UAnMOD register
CHLN bit
STPB bit
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

12.5 Operations

12.5.1 Initialization

The UART2 Ch.n should be initialized with the procedure shown below.
1. Assign the UART2 Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
2. Set the UAnCLK.CLKSRC[1:0] and UAnCLK.CLKDIV[1:0] bits. (Configure operating clock)
3. Configure the following UAnMOD register bits:
- UAnMOD.BRDIV bit
- UAnMOD.INVRX bit
- UAnMOD.INVTX bit
- UAnMOD.PUEN bit
- UAnMOD.OUTMD bit (Enable/disable USOUTn pin open-drain output)
- UAnMOD.IRMD bit
- UAnMOD.CHLN bit
- UAnMOD.PREN bit
- UAnMOD.PRMD bit
- UAnMOD.STPB bit
4. Set the UAnBR.BRT[7:0] and UAnBR.FMD[3:0] bits.
5. Set the following UAnCTL register bits:
- Set the UAnCTL.SFTRST bit to 1.
- Set the UAnCTL.MODEN bit to 1.
6. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the UAnINTF register.
- Set the interrupt enable bits in the UAnINTE register to 1. * (Enable interrupts)
* The initial value of the UAnINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the UA-
nINTE.TBEIE bit is set to 1.
12-4
PREN bit
0
st
D0
1
st
D0
0
st
D0
1
st
D0
0
st
D0
1
st
D0
0
st
D0
1
st
D0
Figure 12.4.1 Data Format
(Select baud rate division ratio (1/16 or 1/4))
(Enable/disable USINn input signal inversion)
(Enable/disable USOUTn output signal inversion)
(Enable/disable USINn pin pull-up)
(Enable/disable IrDA interface)
(Set data length (7 or 8 bits))
(Enable/disable parity function)
(Select parity mode (even or odd))
(Set stop bit length (1 or 2 bits))
Seiko Epson Corporation
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
st: start bit, sp: stop bit, p: parity bit
(Set transfer rate)
(Execute software reset)
(Enable UART2 Ch.n operations)
(Clear interrupt flags)
S1C17W12/W13 TECHNICAL MANUAL
D6
sp
D6
p
sp
D6
sp
sp
D6
p
sp
sp
D6
D7
sp
D6
D7
p
sp
D6
D7
sp
sp
D6
D7
p
sp
sp
(Rev. 1.2)

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