I2C Ch.n Control Register - Epson S1C17W12 Technical Manual

I2C Ch.n Control Register

Register name Bit
I2CnCTL 15–8 –
7–6 –
5
4
3
2
1
0
Bits 15–6 Reserved
Bit 5 MST
This bit selects the I2C Ch.n operating mode.
1 (R/W): Master mode
0 (R/W): Slave mode
Bit 4 TXNACK
This bit issues a request for sending a NACK at the next responding.
1 (W): Issue a NACK.
0 (W): Ineffective
1 (R): On standby or during sending a NACK
0 (R): NACK has been sent.
This bit is automatically cleared after a NACK has been sent.
Bit 3 TXSTOP
This bit issues a STOP condition in master mode. This bit is ineffective in slave mode.
1 (W): Issue a STOP condition.
0 (W): Ineffective
1 (R): On standby or during generating a STOP condition
0 (R): STOP condition has been generated.
This bit is automatically cleared when the bus free time (t
elapsed after the STOP condition has been generated.
Bit 2 TXSTART
This bit issues a START condition in master mode. This bit is ineffective in slave mode.
1 (W): Issue a START condition.
0 (W): Ineffective
1 (R): On standby or during generating a START condition
0 (R): START condition has been generated.
This bit is automatically cleared when a START condition has been generated.
Bit 1 SFTRST
This bit issues software reset to the I2C.
1 (W): Issue software reset
0 (W): Ineffective
1 (R): Software reset is executing.
0 (R): Software reset has finished. (During normal operation)
Setting this bit resets the I2C transmit/receive control circuit and interrupt flags. This bit is automati-
cally cleared after the reset processing has finished.
Bit 0 MODEN
This bit enables the I2C operations.
1 (R/W): Enable I2C operations (The operating clock is supplied.)
0 (R/W): Disable I2C operations (The operating clock is stopped.)
S1C17W12/W13 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
0x0
MST 0
TXNACK 0
TXSTOP 0
TXSTART 0
SFTRST 0
MODEN 0
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W
H0/S0 R/W
H0/S0 R/W
H0/S0 R/W
H0 R/W
H0 R/W
defined in the I
BUF
14 I 2 C (I2C)
Remarks
C Specifications) has
2
14-19