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18 LCD DRIVER (LCD4A)
18.5.2 Display On/Off
The LCD display state is controlled using the LCD4DSP.DSPC[1:0] bits.
Selecting "Display off" stops the drive voltage supply and the LCD driver pin outputs are all set to V
the LCD4CTL.LCDDIS bit = 1.
Since "All on" and "All off" directly control the driving waveform output by the LCD driver, data in the display
data RAM is not altered. The common pins are set to dynamic drive for "All on" and to static drive for "All off."
This function can be used to make the display flash on and off without altering the display memory.
Note: When "Display off" is selected while the external LCD drive voltages are being supplied in an ex-
ternal voltage application mode, the electric charges of V
procedure.
1. Turn the external power supply off.
2. Set the LCD4PWR.EXVCSEL bit to 0.
3. Set the LCD4PWR.EXVCSEL bit to 1.
18.5.3 Inverted Display
The LCD panel display can be inverted (black/white inversion) using merely control bit manipulation, without re-
writing the display data RAM. Setting the LCD4DSP.DSPREV bit to 0 inverts the display; setting it to 1 returns the
display to normal status. Note that the display will not be inverted when the LCD4DSP.DSPC[1:0] bits = 0x3 (All
off).
18.5.4 Drive Duty Switching
Drive duty can be set to 1/4 to 1/2 or static drive using the LCD4TIM1.LDUTY[1:0] bits. Table 18.5.4.1 shows the
correspondence between the LCD4TIM1.LDUTY[1:0] bit settings, drive duty, and maximum number of display
segments.
LCD4TIM1.
LDUTY[1:0] bits
0x3
0x2
0x1
0x0
Unused common pins output an OFF waveform that turns the segments off.
18.5.5 Drive Waveforms
Figures 18.5.5.1 to 18.5.5.4 show drive waveform examples by drive duty.
18-6
Table 18.5.2.1 LCD Display Control
LCD4DSP.DSPC[1:0] bits
0x3
0x2
0x1
0x0
Table 18.5.4.1 Drive Duty Settings
Duty
Valid COM pins
1/4
COM0–3
1/3
COM0–2
1/2
COM0–1
Static
COM0
Seiko Epson Corporation
LCD display
All off (static drive)
All on
Normal display
Display off
must be discharged in the following
C3
(Select internal generation mode)
(Select external voltage application mode)
Valid SEG pins
48pin
64pin/Chip
SEG2–19
SEG0–25
level when
SS
Max. number of
display dots/segments
48pin
64pin/Chip
72
104
54
78
36
52
18
26
S1C17W12/W13 TECHNICAL MANUAL
(Rev. 1.2)
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