Epson S1C17W12 Technical Manual page 316

Treatment of exposed die pad
The exposed die pad of the packages such as QFN has the same potential as that of the substrate on the back of
the IC. When mounting these packages on a circuit board, please note the following:
(1) When soldering exposed die pad to mounting board
Connect the exposed die pad with a wiring pattern that has the same potential as the substrate potential
on the back of the IC, or do not connect it electrically (leave it open electrically). Even if connected to the
same potential on the back of the IC, the power supply pins must be connected to the power source (the ex-
posed die pad cannot be used as a power supply pad).
(2) When not soldering exposed die pad to mounting board
Do not place any signal wiring pattern on the exposed die pad area of the mounting board.
Miscellaneous
Minor variations over time may result in electrical damage arising from disturbances in the form of voltages
exceeding the absolute maximum rating when mounting the product in addition to physical damage. The fol-
lowing factors can give rise to these variations:
(1) Electromagnetically-induced noise from industrial power supplies used in mounting reflow, reworking after
mounting, and individual characteristic evaluation (testing) processes
(2) Electromagnetically-induced noise from a solder iron when soldering
In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po-
tential as the IC GND.
S1C17W12/W13 TECHNICAL MANUAL
(Rev. 1.2)
Seiko Epson Corporation
APPENDIX C MOUNTING PRECAUTIONS
AP-C-3