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Pin
Signal
R3.0: 10G_PHY_CAP_23
D34
R3.1: RSVD10G
R3.0: 10G_PHY_CAP_01
D35
R3.1: CEI_PRSNT#
D36
RSVD
D37
RSVD
R3.0: 10G_SFP_SCL1
D38
R3.1: RSVD10G
R3.0: 10G_SFP_SCL0
D39
R3.1: CEI_SCL
D40
10G_SDP1
D41
GND
D42
10G_KR_TX1+
D43
10G_KR_TX1-
D44
GND
R3.0:
10G_PHY_MDIO_SDA1
D45
R3.1: RSVD10G
D46
R3.0:
10G_PHY_MDIO_SDA0
R3.1: CEI_MDIO
R3.0: 10G_INT1
D47
R3.1: ETH_PHY_INT#
D48
GND
D49
10G_KR_TX0+
D50
10G_KR_TX0-
D51
GND
D52
PCIE_TX16+
D53
PCIE_TX16-
D54
RSVD
D55
PCIE_TX17+
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Description
PHY on ports 2 and 3 mode
capability – I2C or MDIO
Not used
PHY on ports 0 and 1 mode
capability – I2C or MDIO
Presence of CEI compliant
hardware
Reserved for future use
Reserved for future use
Management I2C Clock for
optical SFP Module
Not used
Management I2C Clock for
optical SFP Module
I2C clock for CEI I2C port
Software-Definable Pin
Power Ground
10GBASE-KR Transmit +
10GBASE-KR Transmit -
Power Ground
Management I2C Data for
external PHY
Not used
MDIO data – for external
PHY setup
Interrupt from copper PHY or
optical SFP Module
Interrupt from external I2C
I/O
expander
Power Ground
10GBASE-KR Transmit +
10GBASE-KR Transmit -
Power Ground
PCI Express Lane 16
Transmit +
PCI Express Lane 16
Transmit -
Reserved for future use
PCI Express Lane 17 Transmit
+
COMe-bID7 User Guide Rev. 1.2
Type
Termination / Comment
I-3.3
PU 10k 3.3V (S5)
NC
-
I-3.3
PU 10k 3.3V (S5)
NC
-
NC
-
I/O-3.3
PU 2k2 3.3V (S5)
NC
-
PU 2k2 3.3V (S5)
I/O-3.3
PU 10k 3.3V (S5)
I/O-3.3
-
PWR GND
-
DP-O
-
DP-O
-
PWR GND
-
I/O-3.3
PU 2k2 3.3V (S5)
NC
-
PU 2k2 3.3V (S5)
I/O-3.3
PU 1k 3.3V (S5)
PU 2k2 3.3V (S5)
I-3.3
PU 2k 3.3V (S5)
PWR GND
-
DP-O
-
DP-O
-
PWR GND
-
DP-O
AC Coupled on Module
DP-O
AC Coupled on Module
NC
-
DP-O
AC Coupled on Module
// 63
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