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Pin
Signal
B24
PWR_OK
B25
PCIE_TX14+
B26
PCIE_TX14-
B27
WDT
R3.0: RSVD
B28
R3.1: GND
R3.0: RSVD
B29
R3.1: PCIE1_CK_REF+
R3.0: RSVD
B30
R3.1: PCIE1_CK_REF-
B31
GND
B32
SPKR
B33
I2C_CK
B34
I2C_DAT
B35
THRM#
B36
PCIE_RX13+
B37
PCIE_RX13-
B38
GND
B39
PCIE_RX12+
B40
PCIE_RX12-
B41
GND
B42
USB3-
B43
USB3+
B44
USB_0_1_OC#
B45
USB1-
B46
USB1+
B47
ESPI_EN#
B48
USB0_HOST_PRSNT
B49
SYS_RESET#
B50
CB_RESET#
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Description
Power OK
PCI Express Lane 14 Receive
+
PCI Express Lane 14 Receive
-
Watch Dog Time-Out event
Reserved for future use
Power Ground
Reserved for future use
Reference PCI Express
Clock+
Reserved for future use
Reference PCI Express
Clock-
Power Ground
Speaker
I2C Clock
I2C Data
Over Temperature Input
PCI Express Lane 13 Receive
+
PCI Express Lane 13 Receive
-
Power Ground
PCI Express Lane 12 Receive
+
PCI Express Lane 12 Receive
-
Power Ground
USB 2.0 Data Pair Port 3 –
USB 2.0 Data Pair Port 3 +
USB Overcurrent Indicator
Port 0/1
USB 2.0 Data Pair Port 1 –
USB 2.0 Data Pair Port 1 +
LPC/eSPI mode selection
USB host presence on USB0
Reset Button Input
Carrier Board Reset
COMe-bID7 User Guide Rev. 1.2
Type
Termination / Comment
I-3.3
PU 51K (S5) via diode
DP-I
-
DP-I
-
O-3.3
PD 10K
NC
-
PWR GND
-
NC
-
DP-O
100MHz, for PCIe 4.0 on Lanes 16 to 31
NC
-
DP-O
100MHz, for PCIe 4.0 on Lanes 16 to 31
PWR GND
-
O-3.3
From FPGA
O-3.3
PU 2k2 3.3V (S5)
I/O-3.3
PU 2k2 3.3V (S5)
I-3.3
PU 10k 3.3V (S0)
DP-I
-
DP-I
-
PWR GND
-
DP-I
-
DP-I
-
PWR GND
-
DP-I/O
-
DP-I/O
-
I-3.3
PU 10k 3.3V (S5)
DP-I/O
-
DP-I/O
-
NC
PU 20k 3.3V (S5);
Not supported
NC
Not supported
I-3.3
PU 10k 3.3V (S5)
O-3.3
-
// 54
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