Analog Devices ADSP-BF561 EZ-KIT Lite Manual page 87

synchronous dynamic random access memory,
See SDRAM
system
architecture, of EZ-KIT Lite,
clock (SCLK), 1-9
T
Target Options dialog box,
test DIP switches (SW10-11),
TFS0 signal, 1-11, 2-12
time-division multiplexed (TDM) mode,
timers11-8, 2-6
timers7-0, 2-4
TSCLK0 signal, 1-11, 2-12
U
UART
loop jumper (P1), 2-15
port, xii, 2-8
transmit/receive pins (PF26-27),
universal asynchronous receiver/transmitter, See
UART port
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
www.BDTIC.com/ADI
USB
2-2
user LEDs (LED5-12, LED13-20),
V
1-8 VDDINT signal,
2-13 video
1-11
VisualDSP++
2-5
VROUT pins,
VSYNC signals,
cable, 1-3
interface, 2-9, 2-16, 2-21
monitor LED (ZLED3),
2-14
channels, 2-7, 2-8
configuration switch (SW2),
connector (J6), 2-19
control signals, 2-7, 2-9
decoders, See ADV7183A
encoders, See ADV7179
input (PPI0), 2-8
interface, 1-12
output (PPI1), 2-7
environment, 1-5
online Help, xix
2-14
2-7
INDEX
2-17
2-17
2-10
I-5