Analog Devices ADSP-BF561 EZ-KIT Lite Manual page 31

Settings pull-down menu. The
register values have been set in the
EBIU_SDRRC
in your
VisualDSP\SYSTEM
be changed to be more optimal depending on the
The values in Table 1-2
through the debugger (for example, when viewing memory windows or
loading a program). The numbers are derived for maximum flexibility and
work for a system clock frequency between 60 MHz and 133 MHz.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings
Register
EBIU_SDGCTL
EBIU_SDBCTL
EBIU_SDRRC
The
EBIU_SDGCTL
out of reset. Therefore, the user code should not re-initialize the register.
Clearing the Use XML reset values checkbox allows manual configuration
of the registers. For more information, see online Help.
EBIU
Automatic configuration of SDRAM is not optimized for a specific
frequency. Table 1-3
registers using a 120 MHz
mum frequency when using a 600 MHz core frequency, the
SCLK
maximum frequency for the EZ-KIT Lite. Only the
needs to be modified in the user code to achieve maximum performance.
Table 1-3. SDRAM Optimum Settings
Register
EBIU_SDGCTL
EBIU_SDBCTL
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
www.BDTIC.com/ADI
EBIU_SDGCTL
folder under the
are set by default whenever bank 0 is accessed
Value
0x0091998D
0x00000013
0x000001CF
register can be written once after the processor comes
shows the optimized configuration of the SDRAM
. The frequency of 120 MHz is the maxi-
SCLK
Value
0x0091998D
0x00000013
Using ADSP-BF561 EZ-KIT Lite
,
EBIU_SDBCTL
ADSP-BF561.xml
tag. These values can
RegReset
frequency.
SCLK
Function
Calculated with = 133 MHz
SCLK
Calculated with = 120 MHz
SCLK
EBIU_SDRRC
1
, and
file found
SCLK
register
1-9