Video Interface - Analog Devices ADSP-BF561 EZ-KIT Lite Manual

Video Interface

The AD1836A codec reset is controlled by the processor's programmable
flag . When
PF15
de-asserted. Note that when
AD1836A reset is asserted due to the pull-down resistor. See
ble Flags" on page 2-4
Example programs are included in the EZ-KIT Lite installation
directory to demonstrate the AD1836A codec operation.
Video Interface
The board supports video input and output applications. The ADV7179
video encoder provides up to three output channels of analog video, while
the ADV7183A video decoder provides up to three input channels of ana-
log video. The video encoder connects to the parallel peripheral
interface 1 (
PPI1
eral interface 0, (
configured by the
(SW5)" on page 2-13
Both the encoder and the decoder connect to the parallel peripheral inter-
faces (PPI input clock) of the processor. For additional information on the
video interface hardware, refer to
For the video interface to be operational, the following basic steps must be
performed.
1. Configure the
to "Video Configuration Switch (SW2)" on page 2-10
2. De-assert the video device's reset by setting high a corresponding
programmable flag.
while
PF13
1-12
www.BDTIC.com/ADI
is , the reset is asserted. When
PF15 0
is not driven (configured as input), the
PF15
for more information.
), while the video decoder connects to the parallel periph-
). Each PPI interface has an individual clock that is
PPI0
switch settings. See
SW5
for more information.
"PPI Interfaces" on page
DIP switch as required by the application. Refer
SW2
controls the ADV7179 encoder's reset,
PF14
controls the ADV7183A decoder's reset.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
is
PF15 1
"Programma-
"PPI Clock Select Switch
2-6.
, the reset is
for details.