Analog Devices ADSP-BF561 EZ-KIT Lite Manual page 84

INDEX
core
clock rate, 2-2, 2-14
frequency, 1-9
voltage, 2-2
customer support, xiv
D
DAC A/B/C analog audio channels,
DB9 (UART) connector, xii, 2-8,
default configuration, of this EZ-KIT Lite,
DIP switches
diagram of locations, 1-3,
SW10-11 (test), 2-13
SW2 (video config), 1-12,
SW4 (push button enable), 1-11, 2-12,
E
EBIU
address bus (A25-2) pins,
control signals, 2-3, 2-9
EBIU_SDBCTL register,
EBIU_SDGCTL register,
EBIU_SDRRC register, 1-9,
example programs, 1-13
expansion interface, 2-3, 2-8,
external bus interface unit, See EBIU
external memory
See also flash memory, SDRAM
memory map, 1-7
via JTAG, 2-9
EZ-KIT Extender boards,
F
features, of this EZ-KIT Lite,
FIELD (ADV7183A) control signal, 2-4, 2-8,
2-11
I-2
www.BDTIC.com/ADI
2-7
2-20
1-3
2-10
2-8
2-16
2-3
1-9
1-9
1-10
2-19
2-7
x
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
FIO0_FLAG_D registers,
FIO2_DIR register, 1-10
FIO2_FLAG_C/D/S/T registers,
flag pins, See programmable flags (PFs)
flash
memory, 2-3, 2-11
ports (PB47-32), 2-17
frequency, 1-9
G
general-purpose IO pins, 1-10, 2-4, 2-12,
GND signals, 2-9
H
Help, online, xix
HSYNC signals, 2-6, 2-7
I
input clocks, 1-12, 2-2, 2-6,
installation, of this EZ-KIT Lite,
interfaces, See video, SPORT0, SPI, expansion
internal memory
See also SRAM
map of the processor,
internal voltage (VDDINT),
IO voltage, 2-2
J
JTAG
connector (ZP4), 2-9,
emulation port, 2-9
jumpers
JP1 (ADV7179 clock select),
JP2-3 (VDDINT source select),
P1 (UART loop), 2-15
1-10
1-10
2-16
2-7
1-5
1-8
2-14
2-21
2-14
2-14