System Architecture - Analog Devices ADSP-BF609 EZ-KIT Lite Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-KIT Lite
board (Figure 2-1).
RJ45
CONN
USB
Mini
Conn
ACM
GPIOs
TWI
Expansion Interface III
Serial
Ports
EBIU
Figure 2-1. EZ-KIT Lite Block Diagram
The EZ-KIT Lite is designed to demonstrate the ADSP-BF609 Blackfin
processor's capabilities.
The clock rate can be set up on the fly by the processor. The input clock is
25 MHz. The core clock runs at a maximum of 500 MHz. The default
boot mode for the processor is parallel flash boot.
2-2
Quad SPI 32 MB
Flash Burst Flash
32Mb (16M x 16 )
Ethernet
RMII
10/100
SPI SMC0
PHY
MAC
USB OTG
Circuitry
ADSP-BF609
500 MHz
ADM1032
Dual Core
Temp
349-lead LFBGA
Sensor
0.80mm 19x19mm pkg
SD/MMC
Conn
GP
GPIOs
COUNTER
Rotary
Encoder
Conn
TJA 1041
PBs/LEDs
Transceiver
CAN
PWM
RJ11
Conn
Power
EPPIs
SPI
UART
ADSP-BF609 EZ-KIT Lite Evaluation System Manual
Ext
128 MB
25 MHz Clock
DDR2
Oscillator Test Point/
(64M x 16)
Crystal
48 MHz
DDR2 CLK
Oscillator
Link Port 0/
MPJTAG Out
Conn
CAN JTAG
Link Port 1 /
UART
2.0 Port
MPJTAG In
Conn
DIP
ADM3315
SWTs
RS232
JTAG
DB9
Conn
Conn
3.30V (Adjustable)
5V
Power
PWR
1.80V (Adjustable)
Regulation
IN
1.25V (Adjustable)
Ext
Clock
Test Point/
Crystal