Analog Devices ADSP-BF561 EZ-KIT Lite Manual page 30

Memory Map
CORE A MEMORY MAP
0XFFFF FFFF
CORE MMR REGISTERS
0XFFE0 0000
0XFFC0 0000
RESERVED
0XFFB0 1000
L1 SCRATCHPAD SRAM (4K)
0XFFB0 0000
RESERVED
0XFFA1 4000
L1 INSTRUCTION SRAM/CACHE (16K)
0XFFA1 0000
RESERVED
0XFFA0 4000
L1 INSTRUCTION SRAM (16K)
0XFFA0 0000
RESERVED
0XFF90 8000
L1 DATA BANK B SRAM/CACHE (16K)
0XFF90 4000
L1 DATA BANK B SRAM (16K)
0XFF90 0000
RESERVED
0XFF80 8000
L1 DATA BANK A SRAM/CACHE (16K)
0XFF80 4000
L1 DATA BANK A SRAM (16K)
0XFF80 0000
0XFF70 1000
0XFF70 0000
0XFF61 4000
0XFF61 0000
0XFF60 4000
0XFF60 0000
0XFF50 8000
0XFF50 4000
0XFF50 0000
0XFF40 8000
0XFF40 4000
0XFF40 0000
0XFEB2 0000
0XFEB0 0000
0XEF00 0800
Figure 1-2. ADSP-BF561 Processor Internal Memory Map
The 8 MB of flash memory is organized as 4M x 16 bit and mapped into a
ADSP-BF561 processor's ASYNC memory bank 0. The
select signal connects to the output enable pin of flash memory.
The 64 MB of SDRAM is organized as 16M x 32 bits wide. The proces-
sor's memory select pin
control registers must be initialized in order to access the SDRAM
memory.
When in a VisualDSP++ EZ-KIT Lite session, you can configure the
SDRAM registers automatically by selecting the Use XML reset values
box on the Target Options dialog box, which is accessible through the
1-8
www.BDTIC.com/ADI
CORE B MEMORY MAP
CORE MMR REGISTERS
SYSTEM MMR REGISTERS
RESERVED
L1 SCRATCHPAD SRAM (4K)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K)
RESERVED
L1 INSTRUCTION SRAM (16K)
RESERVED
RESERVED
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
RESERVED
L2 SRAM (128K)
RESERVED
is configured for SDRAM. Three SDRAM
~SMS0
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
RESERVED
memory
~AMS0