Analog Devices ADSP-BF561 EZ-KIT Lite Manual page 83

I INDEX
Numerics
2-wire interface (TWI) mode, 1-11, 1-13,
A
A25-2 address bus pins,
AD1836A audio codecs, 1-11, 2-3, 2-4,
ADV7179 video encoders
video interface, 1-12
clock select jumper (JP1),
configuration switch (SW2),
PPI1 interface, 2-6, 2-7
programmable flags, 2-4
reset, 1-12
ADV7183A video decoders
video interface, 1-12
clock select switch (SW5),
configuration switch (SW2),
PPI0 interface, 2-6, 2-8
programmable flags, 2-4
reset, 1-12
AIN1/4/5 analog video channels,
~AMS0 memory select pins,
analog
audio interface, See SPORT0
video interface, See video interface
architecture, of this EZ-KIT Lite,
ASYNC (asynchronous memory control) banks,
1-7
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
www.BDTIC.com/ADI
2-12
2-3
2-12
2-14
2-10
2-13
2-10
2-8
1-8
2-2
audio
codecs, See AD1836A
connectors (J4-5), 2-19
enable switch (SW12),
interface, See SPORT
B
background telemetry channel (BTC),
bill of materials, A-1
BMODE1-0 (boot mode select) pins,
board schematic (ADSP-BF561),
boot mode select switch (SW3),
C
clock select switch, of PPIs (SW5),
codecs, See AD1836A
configuration, of this EZ-KIT Lite,
connectors
diagram of locations,
DB9 (UART), xii, 2-8
J1-3 (expansion), 2-9,
J4-5 (audio), 2-19
J6 (video), 2-19
J7 (power), 2-20
P2 (RS-232), xi, 2-20
P3 (SPORT1), 2-3, 2-20
P5 (SPI), 2-3, 2-14, 2-21
P9 (SPORT0), 2-20
ZP4 (JTAG), 2-21
contents, of this EZ-KIT Lite package,
2-13
1-14
2-11
B-1
2-11
2-13
1-3
2-18
2-19
1-2
I-1