Ppi Interfaces - Analog Devices ADSP-BF561 EZ-KIT Lite Manual

System Architecture

PPI Interfaces

The ADSP-BF561 processor employs two independent parallel peripheral
interfaces (PPIs),
bi-directional bus consisting of 16 bits of data, a dedicated input clock,
and synchronization signals. The ADSP-BF561 EZ-KIT Lite board uti-
lizes the PPI interfaces for video input and video output.
The interface is configured to input video data from the ADV7183A
PPI0
video decoder device: bits
The interface is configured to output video data to the ADV7179
PPI1
video encoder device: bits
Each PPI interface has a dedicated clock input configured independently
by the switch. The clock source can be one of the following: 27 MHz
SW5
crystal oscillator, ADV7183A video decoder's clock output, or external
clock from the expansion interface. See
on page 2-13 for more information about the switch.
The switch provides a flexible connection between dedicated synchro-
SW2
nization IOs (
SYNC1
and decoder's horizontal and vertical synchronization pins. See
Configuration Switch (SW2)" on page 2-10
the switch. For a detailed description of the ADSP-BF561 processor's PPI
interfaces, refer to the ADSP-BF561 Blackfin Processor Hardware Reference.
Table 2-2 describes the PPI pins of the EZ-KIT Lite board.
Table 2-2. PPI Connections
Processor PPI Pin
bits
PPI0 7–0
bits
PPI1 7–0
PPI0 SYNC1
2-6
www.BDTIC.com/ADI
and . Each PPI interface is a half-duplex,
PPI0 PPI1
connect to the video decoder's data outputs.
7–0
connect to the video encoder's data inputs.
7–0
and of each PPI interface) and the encoder's
SYNC2
Other Processor EZ-KIT Lite Function
Function
ADV7183A data outputs
ADV7179 data inputs
Timer 8 ADV7179
Configuration Switch (SW2)" on page
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
"PPI Clock Select Switch (SW5)"
for more information about
P15–8
P7–0
. For more information, see
HSYNC
"Video
"Video
2-10.